ch2_2_1.hif

《VHDL与数字电路设计》配套光盘,可以实际调用

HIF003
--
-- Copyright (C) 1988-1999 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	lpm_add_sub.tdf
	{
		lpm_add_sub [USE_LPM_FOR_AHDL_OPERATORS,LPM_WIDTH,LPM_REPRESENTATION=SIGNED,LPM_DIRECTION=DEFAULT,ONE_INPUT_IS_CONSTANT=NO,LPM_PIPELINE=0,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY,STYLE] [aglobal.inc,altshift.inc,bypassff.inc,look_add.inc,addcore.inc,lpm_add_sub.inc]
		{
			1 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=2,LPM_REPRESENTATION=SIGNED,LPM_DIRECTION=DEFAULT,ONE_INPUT_IS_CONSTANT=NO,LPM_PIPELINE=0,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K,STYLE=NORMAL] [DATAA0,DATAA1,DATAB0,DATAB1,CIN,RESULT0,RESULT1];
		}
	}
	addcore.tdf
	{
		addcore [USE_LPM_FOR_AHDL_OPERATORS,width,CONSTANT_CIN,CARRY_CHAIN,CARRY_CHAIN_LENGTH,DEVICE_FAMILY] [aglobal.inc,addcore.inc]
		{
			2 [USE_LPM_FOR_AHDL_OPERATORS=OFF,width=2,CONSTANT_CIN=0,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K] [cin,datab0,datab1,dataa0,dataa1,result0,result1];
		}
	}
	altshift.tdf
	{
		altshift [USE_LPM_FOR_AHDL_OPERATORS,WIDTH=4,DEPTH=0] []
		{
			3 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=2,DEPTH=0] [data0,data1,result0,result1];
			4 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=1,DEPTH=0] [data0,result0];
			7 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=4,DEPTH=0] [data0,data1,data2,data3,result0,result1,result2,result3];
		}
	}
	lpm_mult.tdf
	{
		lpm_mult [USE_LPM_FOR_AHDL_OPERATORS,lpm_widtha,lpm_widthb,LPM_WIDTHP,LPM_WIDTHR=0,LPM_WIDTHS,LPM_REPRESENTATION=UNSIGNED,LPM_PIPELINE=0,LATENCY=0,INPUT_A_IS_CONSTANT=NO,INPUT_B_IS_CONSTANT=NO,USE_EAB=OFF,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,DEVICE_FAMILY,CARRY_CHAIN] [altshift.inc,bypassff.inc,multcore.inc,lpm_add_sub.inc,aglobal.inc]
		{
			5 [USE_LPM_FOR_AHDL_OPERATORS=OFF,lpm_widtha=2,lpm_widthb=2,LPM_WIDTHP=4,LPM_WIDTHR=0,LPM_WIDTHS=1,LPM_REPRESENTATION=UNSIGNED,LPM_PIPELINE=0,LATENCY=0,INPUT_A_IS_CONSTANT=NO,INPUT_B_IS_CONSTANT=NO,USE_EAB=OFF,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,DEVICE_FAMILY=FLEX10K,CARRY_CHAIN=IGNORE] [DATAA0,DATAA1,DATAB0,DATAB1,RESULT0,RESULT1,RESULT2,RESULT3];
		}
	}
	multcore.tdf
	{
		multcore [USE_LPM_FOR_AHDL_OPERATORS,LPM_WIDTHA,LPM_WIDTHB,LPM_REPRESENTATION=UNSIGNED,LATENCY=0,ONE_INPUT_IS_CONSTANT=NO,USE_EAB=OFF,MAXIMIZE_SPEED=5,DEVICE_FAMILY,CARRY_CHAIN] [mul_lfrg.inc,muleabz.inc,mpar_add.inc,csa_add.inc,lpm_add_sub.inc,aglobal.inc]
		{
			6 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTHA=2,LPM_WIDTHB=2,LPM_REPRESENTATION=UNSIGNED,LATENCY=1,ONE_INPUT_IS_CONSTANT=NO,USE_EAB=OFF,MAXIMIZE_SPEED=5,DEVICE_FAMILY=FLEX10K,CARRY_CHAIN=IGNORE] [datab0,datab1,dataa0,dataa1,result0,result1,result2,result3];
		}
	}
	ch2_2_1.vhd
	{
		ch2_2_1 [] [U5125632.DLS,U9092257.DLS,U9587408.DLS,U7449008.DLS,U1147235.DLS]
		{
			0 [] [];
		}
	}
}
TREE
{
	ch2_2_1::(0,0):(0): ch2_2_1.vhd;
}