ch9_2_2.rpt

《VHDL与数字电路设计》配套光盘,可以实际调用

-- Equation name is '~1142~1', location is LC6_A8, type is buried.
-- synthesized logic cell 
_LC6_A8  = LCELL( _EQ055);
  _EQ055 = !D5
         # !D6
         # !D7;

-- Node name is ':1142' 
-- Equation name is '_LC1_B9', type is buried 
_LC1_B9  = LCELL( _EQ056);
  _EQ056 =  D4 & !D5 &  D6 &  D7
         # !D4 & !D5 & !D6 &  D7
         # !D4 &  D5 &  D6 & !D7
         #  D4 & !D6 & !D7
         #  D4 &  D5 & !D6;

-- Node name is ':1190' 
-- Equation name is '_LC2_B11', type is buried 
_LC2_B11 = LCELL( _EQ057);
  _EQ057 = !D4 &  D5 &  D6 &  D7
         #  D4 & !D5 & !D6 &  D7
         # !D4 & !D5 &  D6 & !D7;

-- Node name is ':1214' 
-- Equation name is '_LC4_A11', type is buried 
_LC4_A11 = LCELL( _EQ058);
  _EQ058 =  D5 & !D6 & !D7;

-- Node name is '~1229~1' 
-- Equation name is '~1229~1', location is LC2_A11, type is buried.
-- synthesized logic cell 
_LC2_A11 = LCELL( _EQ059);
  _EQ059 = !_LC1_A9 &  _LC8_A11
         # !_LC1_A9 &  _LC2_A12
         # !_LC1_A9 &  _LC4_A11;

-- Node name is ':1230' 
-- Equation name is '_LC2_A4', type is buried 
_LC2_A4  = LCELL( _EQ060);
  _EQ060 = !_LC6_A4
         #  _LC2_A11 & !_LC7_A4 & !_LC8_A4;

-- Node name is ':1238' 
-- Equation name is '_LC2_C7', type is buried 
_LC2_C7  = LCELL( _EQ061);
  _EQ061 =  _LC2_A4 &  _LC6_A8;

-- Node name is ':1393' 
-- Equation name is '_LC5_C10', type is buried 
!_LC5_C10 = _LC5_C10~NOT;
_LC5_C10~NOT = LCELL( _EQ062);
  _EQ062 =  D1
         # !D0
         # !D3
         #  D2;

-- Node name is ':1851' 
-- Equation name is '_LC2_C10', type is buried 
_LC2_C10 = LCELL( _EQ063);
  _EQ063 = !_LC1_C5
         # !_LC4_C10
         # !_LC2_C8;

-- Node name is '~1881~1' 
-- Equation name is '~1881~1', location is LC6_C10, type is buried.
-- synthesized logic cell 
_LC6_C10 = LCELL( _EQ064);
  _EQ064 = !D0 & !D1 & !D2 &  D3
         #  D0 &  D1 &  D2 & !D3;

-- Node name is ':1899' 
-- Equation name is '_LC1_C12', type is buried 
_LC1_C12 = LCELL( _EQ065);
  _EQ065 =  D0 &  D1 &  D2
         # !D1 & !D2 &  D3
         #  D1 &  D2 & !D3
         #  D0 &  D2 & !D3;

-- Node name is '~1946~1' 
-- Equation name is '~1946~1', location is LC1_C5, type is buried.
-- synthesized logic cell 
!_LC1_C5 = _LC1_C5~NOT;
_LC1_C5~NOT = LCELL( _EQ066);
  _EQ066 = !D1 &  D2 &  D3;

-- Node name is ':1949' 
-- Equation name is '_LC1_C7', type is buried 
_LC1_C7  = LCELL( _EQ067);
  _EQ067 = !D0 &  D1 &  D2 &  D3
         #  D0 & !D1 & !D2 &  D3
         # !D0 & !D1 &  D2 & !D3;

-- Node name is ':1973' 
-- Equation name is '_LC3_C10', type is buried 
_LC3_C10 = LCELL( _EQ068);
  _EQ068 =  D1 & !D2 & !D3;

-- Node name is '~1988~1' 
-- Equation name is '~1988~1', location is LC4_C10, type is buried.
-- synthesized logic cell 
_LC4_C10 = LCELL( _EQ069);
  _EQ069 = !D3
         #  D2
         # !D1;

-- Node name is ':1988' 
-- Equation name is '_LC1_C10', type is buried 
_LC1_C10 = LCELL( _EQ070);
  _EQ070 =  _LC4_C10 & !_LC5_C10 &  _LC6_C10
         #  _LC3_C10 &  _LC4_C10 & !_LC5_C10;

-- Node name is '~2045~1' 
-- Equation name is '~2045~1', location is LC2_C1, type is buried.
-- synthesized logic cell 
_LC2_C1  = LCELL( _EQ071);
  _EQ071 =  D0 & !D1 &  D2 &  D3
         # !D0 & !D1 & !D2 &  D3
         # !D0 &  D1 &  D2 & !D3
         #  D0 &  D1 & !D2
         #  D0 & !D2 & !D3;

-- Node name is '~2045~2' 
-- Equation name is '~2045~2', location is LC2_C8, type is buried.
-- synthesized logic cell 
_LC2_C8  = LCELL( _EQ072);
  _EQ072 = !D3
         # !D2
         # !D1;

-- Node name is ':2118' 
-- Equation name is '_LC1_C1', type is buried 
!_LC1_C1 = _LC1_C1~NOT;
_LC1_C1~NOT = LCELL( _EQ073);
  _EQ073 = !_LC3_C7
         # !_LC4_C7 & !_LC6_C1;

-- Node name is ':2169' 
-- Equation name is '_LC2_B21', type is buried 
_LC2_B21 = LCELL( _EQ074);
  _EQ074 =  _LC1_B12 &  _LC2_B5
         #  _LC1_B5 &  _LC2_B5;

-- Node name is ':2370' 
-- Equation name is '_LC5_C1', type is buried 
_LC5_C1  = LCELL( _EQ075);
  _EQ075 =  _LC1_C1 & !_LC3_C7 &  _LC4_C7
         #  _LC1_C1 & !_LC3_C7 &  _LC6_C1
         #  _LC3_C7 & !_LC4_C7 & !_LC6_C1
         # !_LC1_C1 &  _LC3_C7;

-- Node name is ':2376' 
-- Equation name is '_LC7_C1', type is buried 
_LC7_C1  = LCELL( _EQ076);
  _EQ076 =  _LC4_C7 &  _LC6_C1
         #  _LC1_C1 & !_LC4_C7 & !_LC6_C1
         # !_LC1_C1 &  _LC4_C7;

-- Node name is ':2382' 
-- Equation name is '_LC4_C1', type is buried 
_LC4_C1  = LCELL( _EQ077);
  _EQ077 = !_LC1_C1 &  _LC6_C1
         #  _LC1_C1 & !_LC6_C1;

-- Node name is ':2415' 
-- Equation name is '_LC1_B18', type is buried 
!_LC1_B18 = _LC1_B18~NOT;
_LC1_B18~NOT = LCELL( _EQ078);
  _EQ078 = !_LC2_B21
         # !_LC1_C1;

-- Node name is ':2417' 
-- Equation name is '_LC1_B20', type is buried 
_LC1_B20 = LCELL( _EQ079);
  _EQ079 = !_LC1_C1 &  _LC2_B21;

-- Node name is ':2419' 
-- Equation name is '_LC1_B22', type is buried 
!_LC1_B22 = _LC1_B22~NOT;
_LC1_B22~NOT = LCELL( _EQ080);
  _EQ080 =  _LC2_B21
         # !_LC1_C1;

-- Node name is ':2535' 
-- Equation name is '_LC1_B15', type is buried 
_LC1_B15 = LCELL( _EQ081);
  _EQ081 =  _LC1_B12 &  _LC1_B20 & !_LC2_B5
         #  _LC1_B5 &  _LC1_B20 & !_LC2_B5
         # !_LC1_B5 & !_LC1_B12 &  _LC1_B20 &  _LC2_B5;

-- Node name is ':2536' 
-- Equation name is '_LC2_B15', type is buried 
_LC2_B15 = LCELL( _EQ082);
  _EQ082 = !_LC1_B20 &  _LC1_B22 & !_LC2_B5 &  _LC4_B15
         # !_LC1_B20 &  _LC2_B5 & !_LC4_B15
         # !_LC1_B20 & !_LC1_B22 &  _LC2_B5;

-- Node name is ':2540' 
-- Equation name is '_LC6_B15', type is buried 
_LC6_B15 = LCELL( _EQ083);
  _EQ083 = !_LC1_B18 &  _LC2_B15
         #  _LC1_B15 & !_LC1_B18
         #  _LC1_B18 &  _LC3_B15;

-- Node name is ':2546' 
-- Equation name is '_LC2_B14', type is buried 
_LC2_B14 = LCELL( _EQ084);
  _EQ084 =  _LC1_B5 & !_LC1_B22
         # !_LC1_B5 &  _LC1_B12 &  _LC1_B19 &  _LC1_B22
         #  _LC1_B5 & !_LC1_B19
         #  _LC1_B5 & !_LC1_B12;

-- Node name is ':2549' 
-- Equation name is '_LC1_B14', type is buried 
_LC1_B14 = LCELL( _EQ085);
  _EQ085 = !_LC1_B20 &  _LC2_B14
         #  _LC1_B5 &  _LC1_B12 &  _LC1_B20
         # !_LC1_B5 & !_LC1_B12 &  _LC1_B20;

-- Node name is ':2552' 
-- Equation name is '_LC5_B14', type is buried 
_LC5_B14 = LCELL( _EQ086);
  _EQ086 =  _LC1_B14 & !_LC1_B18
         #  _LC1_B5 &  _LC1_B18 &  _LC3_B14
         # !_LC1_B5 &  _LC1_B18 & !_LC3_B14;

-- Node name is ':2564' 
-- Equation name is '_LC3_B16', type is buried 
_LC3_B16 = LCELL( _EQ087);
  _EQ087 =  _LC1_B12 &  _LC1_B19 &  _LC1_C1 &  _LC2_B21
         # !_LC1_B12 & !_LC1_B19 &  _LC2_B21
         # !_LC1_B12 & !_LC1_C1 &  _LC2_B21
         # !_LC1_B12 &  _LC1_B19 &  _LC1_C1 & !_LC2_B21
         #  _LC1_B12 & !_LC1_B19 & !_LC2_B21
         #  _LC1_B12 & !_LC1_C1 & !_LC2_B21;

-- Node name is ':2576' 
-- Equation name is '_LC3_B17', type is buried 
_LC3_B17 = LCELL( _EQ088);
  _EQ088 =  _LC1_B18 & !_LC1_B19
         # !_LC1_B19 & !_LC1_B20 &  _LC1_B22
         # !_LC1_B18 &  _LC1_B19 & !_LC1_B22
         # !_LC1_B18 &  _LC1_B19 &  _LC1_B20;

-- Node name is ':2734' 
-- Equation name is '_LC7_B3', type is buried 
_LC7_B3  = LCELL( _EQ089);
  _EQ089 =  _LC1_B3 &  _LC2_B3 &  _LC2_B21
         #  _LC1_A6;

-- Node name is ':2746' 
-- Equation name is '_LC6_B3', type is buried 
_LC6_B3  = LCELL( _EQ090);
  _EQ090 = !_LC1_A6 & !_LC1_B3 &  _LC2_B3
         # !_LC1_A6 &  _LC1_B3 & !_LC2_B3 &  _LC2_B21
         # !_LC1_A6 &  _LC2_B3 & !_LC2_B21;

-- Node name is ':2758' 
-- Equation name is '_LC5_B3', type is buried 
_LC5_B3  = LCELL( _EQ091);
  _EQ091 = !_LC1_A6 &  _LC1_B3 & !_LC2_B21
         # !_LC1_B3 &  _LC2_B21
         #  _LC1_A6 &  _LC2_B21;



Project Information               d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:02
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:08
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:16


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,519K