ch9_2_3.rpt

《VHDL与数字电路设计》配套光盘,可以实际调用

Project Information               d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_3.rpt

MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 06/15/2000 18:10:56

Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


CH9_2_3


** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

ch9_2_3   EPF10K10TC144-3  11     18     0    0         0  %    174      30 %

User Pins:                 11     18     0  



Project Information               d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_3.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

ch9_2_3@55                        CP
ch9_2_3@131                       Din0
ch9_2_3@132                       Din1
ch9_2_3@133                       Din2
ch9_2_3@135                       Din3
ch9_2_3@136                       Din4
ch9_2_3@137                       Din5
ch9_2_3@138                       Din6
ch9_2_3@140                       Din7
ch9_2_3@38                        nCS
ch9_2_3@143                       nINTR
ch9_2_3@128                       nRD
ch9_2_3@124                       RST
ch9_2_3@23                        SEGOUT0
ch9_2_3@26                        SEGOUT1
ch9_2_3@27                        SEGOUT2
ch9_2_3@28                        SEGOUT3
ch9_2_3@29                        SEGOUT4
ch9_2_3@30                        SEGOUT5
ch9_2_3@31                        SEGOUT6
ch9_2_3@32                        SEGOUT7
ch9_2_3@33                        SELOUT0
ch9_2_3@36                        SELOUT1
ch9_2_3@37                        SELOUT2


Project Information               d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_3.rpt

** STATE MACHINE ASSIGNMENTS **


State: MACHINE
        OF BITS (
           State~4,
           State~3,
           State~2,
           State~1
        )
        WITH STATES (
                              S0 = B"0000", 
                              S1 = B"1100", 
                              S2 = B"1010", 
                              S3 = B"1001"
);



Project Information               d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_3.rpt

** FILE HIERARCHY **



|lpm_add_sub:504|
|lpm_add_sub:504|addcore:adder|
|lpm_add_sub:504|altshift:result_ext_latency_ffs|
|lpm_add_sub:504|altshift:carry_ext_latency_ffs|
|lpm_add_sub:504|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2304|
|lpm_add_sub:2304|addcore:adder|
|lpm_add_sub:2304|altshift:result_ext_latency_ffs|
|lpm_add_sub:2304|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2304|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2355|
|lpm_add_sub:2355|addcore:adder|
|lpm_add_sub:2355|altshift:result_ext_latency_ffs|
|lpm_add_sub:2355|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2355|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2406|
|lpm_add_sub:2406|addcore:adder|
|lpm_add_sub:2406|altshift:result_ext_latency_ffs|
|lpm_add_sub:2406|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2406|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2527|
|lpm_add_sub:2527|addcore:adder|
|lpm_add_sub:2527|altshift:result_ext_latency_ffs|
|lpm_add_sub:2527|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2527|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2528|
|lpm_add_sub:2528|addcore:adder|
|lpm_add_sub:2528|altshift:result_ext_latency_ffs|
|lpm_add_sub:2528|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2528|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2549|
|lpm_add_sub:2549|addcore:adder|
|lpm_add_sub:2549|altshift:result_ext_latency_ffs|
|lpm_add_sub:2549|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2549|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2633|
|lpm_add_sub:2633|addcore:adder|
|lpm_add_sub:2633|altshift:result_ext_latency_ffs|
|lpm_add_sub:2633|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2633|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2634|
|lpm_add_sub:2634|addcore:adder|
|lpm_add_sub:2634|altshift:result_ext_latency_ffs|
|lpm_add_sub:2634|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2634|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2659|
|lpm_add_sub:2659|addcore:adder|
|lpm_add_sub:2659|altshift:result_ext_latency_ffs|
|lpm_add_sub:2659|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2659|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2660|
|lpm_add_sub:2660|addcore:adder|
|lpm_add_sub:2660|altshift:result_ext_latency_ffs|
|lpm_add_sub:2660|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2660|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2685|
|lpm_add_sub:2685|addcore:adder|
|lpm_add_sub:2685|altshift:result_ext_latency_ffs|
|lpm_add_sub:2685|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2685|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2686|
|lpm_add_sub:2686|addcore:adder|
|lpm_add_sub:2686|altshift:result_ext_latency_ffs|
|lpm_add_sub:2686|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2686|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2707|
|lpm_add_sub:2707|addcore:adder|
|lpm_add_sub:2707|altshift:result_ext_latency_ffs|
|lpm_add_sub:2707|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2707|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2821|
|lpm_add_sub:2821|addcore:adder|
|lpm_add_sub:2821|altshift:result_ext_latency_ffs|
|lpm_add_sub:2821|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2821|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2822|
|lpm_add_sub:2822|addcore:adder|
|lpm_add_sub:2822|altshift:result_ext_latency_ffs|
|lpm_add_sub:2822|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2822|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2847|
|lpm_add_sub:2847|addcore:adder|
|lpm_add_sub:2847|altshift:result_ext_latency_ffs|
|lpm_add_sub:2847|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2847|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2848|
|lpm_add_sub:2848|addcore:adder|
|lpm_add_sub:2848|altshift:result_ext_latency_ffs|
|lpm_add_sub:2848|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2848|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2873|
|lpm_add_sub:2873|addcore:adder|
|lpm_add_sub:2873|altshift:result_ext_latency_ffs|
|lpm_add_sub:2873|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2873|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2874|
|lpm_add_sub:2874|addcore:adder|
|lpm_add_sub:2874|altshift:result_ext_latency_ffs|
|lpm_add_sub:2874|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2874|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2895|
|lpm_add_sub:2895|addcore:adder|
|lpm_add_sub:2895|altshift:result_ext_latency_ffs|
|lpm_add_sub:2895|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2895|altshift:oflow_ext_latency_ffs|


Device-Specific Information:      d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_3.rpt
ch9_2_3

***** Logic for device 'ch9_2_3' compiled without errors.




Device: EPF10K10TC144-3

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f
    MultiVolt I/O                              = OFF

                                                                                         
                                                                                         
                R   R R                     R               R R R R R R R   R R R   R R  
                E   E E                     E               E E E E E E E   E E E   E E  
                S   S S                     S     G G G   V S S S S S S S   S S S   S S  
                E n E E   G         V       E G   N N N   C E E E E E E E V E E E D E E  
                R I R R D N D D D D C D D D R N   D D D   C R R R R R R R C R R R o R R  
                V N V V i D i i i i C i i i V D n I I I R I V V V V V V V C V V V u V V  
                E T E E n I n n n n I n n n E I R N N N S N E E E E E E E I E E E t E E  
                D R D D 7 O 6 5 4 3 O 2 1 0 D O D T T T T T D D D D D D D O D D D 3 D D  
              --------------------------------------------------------------------------_ 
             / 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110   |_ 
            /    143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109    | 
      #TCK |  1                                                                         108 | ^DATA0 
^CONF_DONE |  2                                                                         107 | ^DCLK 
     ^nCEO |  3                                                                         106 | ^nCE 
      #TDO |  4                                                                         105 | #TDI 
     VCCIO |  5                                                                         104 | GNDIO 
    VCCINT |  6                                                                         103 | GNDINT 
  RESERVED |  7                                                                         102 | RESERVED 
  RESERVED |  8                                                                         101 | RESERVED 
  RESERVED |  9                                                                         100 | RESERVED 
  RESERVED | 10                                                                          99 | RESERVED 
       nWR | 11                                                                          98 | RESERVED 
  RESERVED | 12                                                                          97 | RESERVED 
  RESERVED | 13                                                                          96 | RESERVED 
  RESERVED | 14                                                                          95 | RESERVED 
     GNDIO | 15                                                                          94 | VCCIO 
    GNDINT | 16                                                                          93 | VCCINT 
  RESERVED | 17                                                                          92 | RESERVED 
  RESERVED | 18                                                                          91 | RESERVED 
  RESERVED | 19                             EPF10K10TC144-3                              90 | RESERVED 
  RESERVED | 20                                                                          89 | RESERVED 
  RESERVED | 21                                                                          88 | RESERVED 
  RESERVED | 22                                                                          87 | RESERVED 
   SEGOUT0 | 23                                                                          86 | RESERVED 
     VCCIO | 24                                                                          85 | GNDIO 
    VCCINT | 25                                                                          84 | GNDINT 
   SEGOUT1 | 26                                                                          83 | Dout0 
   SEGOUT2 | 27                                                                          82 | Dout2 
   SEGOUT3 | 28                                                                          81 | Dout1