📄 ch9_2_1.rpt
字号:
- 5 - A 06 DFFE + 1 1 1 0 D2 (:32)
- 7 - A 05 DFFE + 1 1 1 0 D1 (:33)
- 7 - A 04 DFFE + 1 1 1 0 D0 (:34)
- 2 - A 01 DFFE + 0 3 0 8 EC (:35)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_1.rpt
ch9_2_1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 9/ 48( 18%) 0/ 48( 0%) 5/16( 31%) 11/16( 68%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_1.rpt
ch9_2_1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 CP
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_1.rpt
ch9_2_1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 RST
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_1.rpt
ch9_2_1
** EQUATIONS **
CP : INPUT;
Din0 : INPUT;
Din1 : INPUT;
Din2 : INPUT;
Din3 : INPUT;
Din4 : INPUT;
Din5 : INPUT;
Din6 : INPUT;
Din7 : INPUT;
nINTR : INPUT;
RST : INPUT;
-- Node name is 'Dout0'
-- Equation name is 'Dout0', type is output
Dout0 = D0;
-- Node name is 'Dout1'
-- Equation name is 'Dout1', type is output
Dout1 = D1;
-- Node name is 'Dout2'
-- Equation name is 'Dout2', type is output
Dout2 = D2;
-- Node name is 'Dout3'
-- Equation name is 'Dout3', type is output
Dout3 = D3;
-- Node name is 'Dout4'
-- Equation name is 'Dout4', type is output
Dout4 = D4;
-- Node name is 'Dout5'
-- Equation name is 'Dout5', type is output
Dout5 = D5;
-- Node name is 'Dout6'
-- Equation name is 'Dout6', type is output
Dout6 = D6;
-- Node name is 'Dout7'
-- Equation name is 'Dout7', type is output
Dout7 = D7;
-- Node name is ':34' = 'D0'
-- Equation name is 'D0', location is LC7_A4, type is buried.
D0 = DFFE( _EQ001, GLOBAL( CP), VCC, VCC, VCC);
_EQ001 = Din0 & EC
# D0 & !EC;
-- Node name is ':33' = 'D1'
-- Equation name is 'D1', location is LC7_A5, type is buried.
D1 = DFFE( _EQ002, GLOBAL( CP), VCC, VCC, VCC);
_EQ002 = Din1 & EC
# D1 & !EC;
-- Node name is ':32' = 'D2'
-- Equation name is 'D2', location is LC5_A6, type is buried.
D2 = DFFE( _EQ003, GLOBAL( CP), VCC, VCC, VCC);
_EQ003 = Din2 & EC
# D2 & !EC;
-- Node name is ':31' = 'D3'
-- Equation name is 'D3', location is LC1_A7, type is buried.
D3 = DFFE( _EQ004, GLOBAL( CP), VCC, VCC, VCC);
_EQ004 = Din3 & EC
# D3 & !EC;
-- Node name is ':30' = 'D4'
-- Equation name is 'D4', location is LC2_A2, type is buried.
D4 = DFFE( _EQ005, GLOBAL( CP), VCC, VCC, VCC);
_EQ005 = Din4 & EC
# D4 & !EC;
-- Node name is ':29' = 'D5'
-- Equation name is 'D5', location is LC1_A2, type is buried.
D5 = DFFE( _EQ006, GLOBAL( CP), VCC, VCC, VCC);
_EQ006 = Din5 & EC
# D5 & !EC;
-- Node name is ':28' = 'D6'
-- Equation name is 'D6', location is LC7_A2, type is buried.
D6 = DFFE( _EQ007, GLOBAL( CP), VCC, VCC, VCC);
_EQ007 = Din6 & EC
# D6 & !EC;
-- Node name is ':27' = 'D7'
-- Equation name is 'D7', location is LC7_A3, type is buried.
D7 = DFFE( _EQ008, GLOBAL( CP), VCC, VCC, VCC);
_EQ008 = Din7 & EC
# D7 & !EC;
-- Node name is ':35' = 'EC'
-- Equation name is 'EC', location is LC2_A1, type is buried.
EC = DFFE( _EQ009, GLOBAL( CP), GLOBAL(!RST), VCC, VCC);
_EQ009 = State~2 & !State~3 & State~4;
-- Node name is 'nCS'
-- Equation name is 'nCS', type is output
nCS = _LC4_A1;
-- Node name is 'nRD'
-- Equation name is 'nRD', type is output
nRD = _LC6_A1;
-- Node name is 'nWR'
-- Equation name is 'nWR', type is output
nWR = _LC5_A1;
-- Node name is 'State~1'
-- Equation name is 'State~1', location is LC8_A1, type is buried.
State~1 = DFFE( State~2, GLOBAL( CP), GLOBAL(!RST), VCC, VCC);
-- Node name is 'State~2'
-- Equation name is 'State~2', location is LC7_A1, type is buried.
State~2 = DFFE( _EQ010, GLOBAL( CP), GLOBAL(!RST), VCC, VCC);
_EQ010 = !nINTR & State~3;
-- Node name is 'State~3'
-- Equation name is 'State~3', location is LC3_A1, type is buried.
State~3 = DFFE( _EQ011, GLOBAL( CP), GLOBAL(!RST), VCC, VCC);
_EQ011 = !State~4
# nINTR & State~3;
-- Node name is 'State~4'
-- Equation name is 'State~4', location is LC1_A1, type is buried.
State~4 = DFFE(!State~1, GLOBAL( CP), GLOBAL(!RST), VCC, VCC);
-- Node name is ':19'
-- Equation name is '_LC4_A1', type is buried
!_LC4_A1 = _LC4_A1~NOT;
_LC4_A1~NOT = DFFE( _EQ012, GLOBAL( CP), GLOBAL(!RST), VCC, VCC);
_EQ012 = State~2 & !State~3
# !State~4;
-- Node name is ':21'
-- Equation name is '_LC5_A1', type is buried
!_LC5_A1 = _LC5_A1~NOT;
_LC5_A1~NOT = DFFE(!State~4, GLOBAL( CP), GLOBAL(!RST), VCC, VCC);
-- Node name is ':23'
-- Equation name is '_LC6_A1', type is buried
!_LC6_A1 = _LC6_A1~NOT;
_LC6_A1~NOT = DFFE( _EQ013, GLOBAL( CP), GLOBAL(!RST), VCC, VCC);
_EQ013 = State~2 & !State~3 & State~4;
Project Information d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,249K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -