ch5_3_1.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

--*********************************************************
-- 4 BITS ALU : check 4-BIT LOGIC OPERATOR
--*********************************************************
--
entity CH5_3_1 is
     port
     (    A : in UNSIGNED (3 downto 0);
          B : in UNSIGNED (3 downto 0);
		  S : in STD_LOGIC_VECTOR (2 downto 0) ;
          BCDout :  out STD_LOGIC_VECTOR (3 downto 0) 
           );
end CH5_3_1;
--*********************************************************
architecture ARCH of CH5_3_1 is
	signal Y: STD_LOGIC_VECTOR(3 downto 0) ;
BEGIN 

PROCESS (A,B,S)
BEGIN
	CASE S IS

	when "100" =>	
		Y(3) <= A(3) and B(3) ;
		Y(2) <= A(2) and B(2) ;
		Y(1) <= A(1) and B(1) ;
		Y(0) <= A(0) and B(0) ;
	BCDout <= y(3)&Y(2)&Y(1)&Y(0);

	when "101" =>	
		Y(3) <= A(3) or B(3) ;
		Y(2) <= A(2) or B(2) ;
		Y(1) <= A(1) or B(1) ;
		Y(0) <= A(0) or B(0) ;
		BCDout <= y(3)&Y(2)&Y(1)&Y(0);

	when "110" =>	
		Y(3) <= A(3) XOR B(3) ;
		Y(2) <= A(2) XOR B(2) ;
		Y(1) <= A(1) XOR B(1) ;
		Y(0) <= A(0) XOR B(0) ;
	BCDout <= y(3)&Y(2)&Y(1)&Y(0);

	when "111" =>	
		Y(3) <= NOT A(3)  ;
		Y(2) <= NOT A(2)  ;
		Y(1) <= NOT A(1)  ;
		Y(0) <= NOT A(0)  ;
	BCDout <= Y(3)&Y(2)&Y(1)&Y(0);

	when others =>
		BCDout <= "0000" ;

	END CASE ;
END PROCESS;
end ARCH;



--*********************************************************