ch5_4_1.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 118 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

--*********************************************************
-- 4 BITS ALU : check 4-BIT MATH  or LOGIC OPERATOR
--*********************************************************
--
entity CH5_4_1 is
     port
     (    A : in UNSIGNED (3 downto 0);
          B : in UNSIGNED (3 downto 0);
		  Cin : in STD_LOGIC ;
		  S : in STD_LOGIC_VECTOR (2 downto 0) ;
          BCDout :  out STD_LOGIC_VECTOR (3 downto 0) ;
          Cout : out STD_LOGIC 
     );
end CH5_4_1;

architecture ARCH of CH5_4_1 is
     SIGNAL C,Y : STD_LOGIC_VECTOR (3 downto 0) ;
     SIGNAL Q : UNSIGNED (3 downto 0) ;


--
--*********************************************************
-- MATH operator
--
begin 

process(S)
	begin 

	case S is
		when "000" =>	--ADDER ;
			Y(0) <= A(0) XOR B(0) XOR Cin ;
			C(0) <= (A(0) AND B(0)) OR (B(0) AND Cin) OR (A(0) AND Cin);
	 	 	GEN1 : FOR I IN 1 TO 3 LOOP
	              Y(I) <= A(I) XOR B(I) XOR C(I-1) ;
	              C(I) <= (C(I-1) AND A(I))  OR (C(I-1) AND B(I)) OR (A(I) AND B(I));
	        END LOOP ;
			BCDout <= Y(3) & Y(2) & Y(1) & Y(0) ;
			Cout <= C(3) ;
		    
		when "001" =>    --SUB ;
			Y(0) <= A(0) XOR B(0) XOR Cin ;
     		C(0) <= (Cin AND NOT A(0))  OR (Cin AND B(0)) OR (NOT A(0) AND B(0));
			GEN2: FOR I IN 1 TO 3 LOOP
			     Y(I) <= A(I) XOR B(I) XOR C(I-1);
			     C(I) <= (C(I-1) AND NOT A(I))  OR (C(I-1) AND B(I)) OR (NOT A(I) AND B(I));
		    END LOOP ;
			BCDout <=  Y(3) & Y(2) & Y(1) & Y(0) ;
			Cout <= C(3) ;
  
		when "010" =>     --TRANSFER A+Cin ;
			IF Cin='0' THEN   
				BCDout  <= A(3) & A(2)  & A(1)  & A(0) ;
			ELSE
 				BCDout  <= A + 1 ;
			END IF ;
   			Cout <= '0' ;

	
		when "011" =>     --TRANSFER A-Cin ;
			IF Cin='1' THEN   
				BCDout  <= A(3) & A(2)  & A(1)  & A(0) ;
			ELSE
 				BCDout  <= A - 1 ;
			END IF ;
   			Cout <= '0' ;


        when "100" =>     -- AND ;
			Y(3) <= A(3) and B(3) ;
			Y(2) <= A(2) and B(2) ;
			Y(1) <= A(1) and B(1) ;
			Y(0) <= A(0) and B(0) ;
			BCDout <= Y(3) & Y(2) & Y(1) & Y(0) ;
		Cout <= '0';


		when "101" =>     -- OR ;	
			Y(3) <= A(3) or B(3) ;
			Y(2) <= A(2) or B(2) ;
			Y(1) <= A(1) or B(1) ;
			Y(0) <= A(0) or B(0) ;
		BCDout <= Y(3) & Y(2) & Y(1) & Y(0) ;
		Cout <= '0';


		when "110" =>     -- XOR ;	
			Y(3) <= A(3) XOR B(3) ;
			Y(2) <= A(2) XOR B(2) ;
			Y(1) <= A(1) XOR B(1) ;
			Y(0) <= A(0) XOR B(0) ;
		Q <= Y(3) & Y(2) & Y(1) & Y(0);
		BCDout <= Y(3) & Y(2) & Y(1) & Y(0);
		Cout <= '0';

		when "111" =>     -- NOT ;	
			Y(3) <= NOT A(3)  ;
			Y(2) <= NOT A(2)  ;
			Y(1) <= NOT A(1)  ;
			Y(0) <= NOT A(0)  ;
    	BCDout <= Y(3) & Y(2) & Y(1) & Y(0) ;
		Cout <= '0';

		when others =>
		BCDout <= "0000" ;
		Cout <= '0';

	END CASE ;
END PROCESS;
end ARCH;