ch4_4_1.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 32 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY CH4_4_1 IS
	PORT (  A:    IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			B:    IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			CLK:  IN STD_LOGIC;
			RST: IN STD_LOGIC;
			AGTB: OUT STD_LOGIC;
			ALTB: OUT STD_LOGIC;
			AEQB: OUT STD_LOGIC);
END CH4_4_1;

ARCHITECTURE arch OF CH4_4_1 IS 
BEGIN
	PROCESS (RST,CLK)
	BEGIN
		IF RST = '1' THEN
			AGTB <= '0';  AEQB <= '0';  ALTB <= '0';
		ELSIF CLK'EVENT AND CLK = '1' THEN
			IF A > B THEN
				AGTB <= '1';  AEQB <= '0';  ALTB <= '0';
			ELSIF a = b THEN
				AGTB <= '0';  AEQB <= '1';  ALTB <= '0';
			else
				AGTB <= '0';  AEQB <= '0';  ALTB <= '1';
			END IF;
		END IF;
	END PROCESS;
END ARCH ;