ch4_2_2.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

LIBRARY  IEEE ;                      
USE  IEEE.STD_LOGIC_1164.ALL ;     
USE  IEEE.STD_LOGIC_ARITH.ALL ;
USE  IEEE.STD_LOGIC_UNSIGNED.ALL ;

--**********************************
ENTITY  ch4_-_2 IS
  PORT (Z  : IN  STD_LOGIC_VECTOR( 3 DOWNTO 0) ;            
        S : IN STD_LOGIC_VECTOR( 1 DOWNTO 0) ;                
        A, B, C, D :  OUT  STD_LOGIC_VECTOR( 3 DOWNTO 0 ) ) ;  
END  ch4_-_2 ;

--**********************************
ARCHITECTURE  demux4_behave  OF  ch4_-_2  IS

BEGIN
  PROCESS (Z,S)

  BEGIN
A <= "0000" ; B <= "0000" ; C <= "0000" ; D <= "0000" ;
    CASE S IS
        WHEN "00" => A <= Z ;
        WHEN "01" => B <= Z ;
        WHEN "10" => C <= Z ;
        WHEN OTHERS  => D <= Z ;
    END CASE ; 
  END PROCESS ;
END demux4_behave ;