ch4_3_1.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

LIBRARY  IEEE ; 
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
--****************************************
ENTITY CH4_3_1 IS
	PORT(	A : IN UNSIGNED( 3 downto 0 )	;
			BCD0, BCD1 : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0) ; 
			SEVEN0 , SEVEN1 : out STD_LOGIC_VECTOR( 6 downto 0 ) 
		) ;
END CH4_3_1 ;
--****************************************
ARCHITECTURE A OF CH4_3_1 IS
SIGNAL XC : STD_LOGIC_VECTOR( 3 DOWNTO 0) ;
BEGIN
   PROCESS (A)
	BEGIN
		IF A<10 THEN
			BCD1 <= "0000" ;
			BCD0<=STD_LOGIC_VECTOR(A) ;
			SEVEN1 <= "0111111" ;
--****************************************
			XC<=STD_LOGIC_VECTOR(A) ;
--****************************************
		ELSE
			BCD1 <= "0001" ;
			BCD0 <= A-10 ;
			SEVEN1 <= "0000110" ;
--****************************************
		XC <= STD_LOGIC_VECTOR(A)-10 ;
--****************************************
		END IF ; 
	END PROCESS ;

	SEVEN_SEGMENT : BLOCK
	BEGIN
	SEVEN0 <= "0111111" WHEN XC= "0000" ELSE	--0
			  "0000110" WHEN XC= "0001" ELSE	--1
			  "1011011" WHEN XC= "0010" ELSE	--2
			  "1001111" WHEN XC= "0011" ELSE	--3
			  "1100110" WHEN XC= "0100" ELSE	--4
			  "1101101" WHEN XC= "0101" ELSE	--5
			  "1111101" WHEN XC= "0110" ELSE	--6
			  "0000111" WHEN XC= "0111" ELSE	--7
			  "1111111" WHEN XC= "1000" ELSE	--8
			  "1101111" WHEN XC= "1001" ELSE	--9
			  "0000000" ;
	END BLOCK SEVEN_SEGMENT ;
END A ;