ch4_1_1.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 32 行

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;

ENTITY CH4_1_1 IS
  PORT (A : IN STD_LOGIC_VECTOR( 2 DOWNTO 0) ;
        EN       : IN STD_LOGIC ;
        Y  : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0)) ;
END CH4_1_1 ;

ARCHITECTURE  DEC_BEHAVE OF CH4_1_1 IS
SIGNAL  SEL : STD_LOGIC_VECTOR( 3 DOWNTO 0) ;
BEGIN

   SEL(0) <= EN ;
   SEL(1) <= A(0) ;
   SEL(2) <= A(1) ;
   SEL(3) <= A(2) ;
   
   WITH SEL SELECT 
     Y<= "00000001" WHEN "0001",
         "00000010" WHEN "0011",
         "00000100" WHEN "0101",
         "00001000" WHEN "0111",
         "00010000" WHEN "1001",
         "00100000" WHEN "1011",
         "01000000" WHEN "1101",
         "10000000" WHEN "1111",
         "11111111" WHEN OTHERS ;
END DEC_BEHAVE ;