ch4_1_2.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 28 行

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;

ENTITY  CH4_1_2  IS
  PORT (A : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
        EN       : IN STD_LOGIC ;
        Y  : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0)) ;
END CH4_1_2 ;

ARCHITECTURE  ENDEC_BEHAVE OF CH4_1_2 IS
SIGNAL  SEL : STD_LOGIC_VECTOR( 8 DOWNTO 0) ;
BEGIN
     
   SEL <= EN  &  A ;

   WITH SEL SELECT 
     Y<= "000" WHEN "100000001" ,
         "001" WHEN "100000010" ,
         "010" WHEN "100000100" ,
         "011" WHEN "100001000" ,
         "100" WHEN "100010000" ,
         "101" WHEN "100100000" ,
         "110" WHEN "101000000" ,
         "111" WHEN "110000000" ,
         "000" WHEN OTHERS ;
END ENDEC_BEHAVE ;