ahour.vhd

来自「这是一个用VHDL写的小程序」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ahour is
port(en,mode     :in std_logic;
   h1,h0         :out std_logic_vector(3 downto 0));
end ahour;
architecture hour_arc of ahour is
begin
process(en,mode)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
	if en'event and en='1'then
		if mode='1'then
			if cnt1="0010"and cnt0="0011"then
				cnt0:="0000";
				cnt1:="0000";
			elsif cnt0<"1001"then
				cnt0:=cnt0+1;
			else
				cnt0:="0000";
				cnt1:=cnt1+1;
			end if;
			end if;
			end if;
h1<=cnt1;
h0<=cnt0;
end process;
end hour_arc;