ts_zdbs.vhd

这是一个用VHDL写的小程序

library ieee;
use ieee.std_logic_1164.all;
entity ts_zdbs is
 port(m1,m0,s1,s0             :in  std_logic_vector(3 downto 0);
      clk                     :in  std_logic;
      q512,q1024              :out std_logic);
end ts_zdbs;
architecture art of ts_zdbs is
begin
   process(clk)
 begin
   if clk'event and clk='1'then
 if m1="0101"and m0="1001"and s1="0101"then
    if s0="0001"or s0="0011"or s0="0101"or s0="0111"then
 q512<='1';
else
    q512<='0';
end if;
end if;
  if m1="0101"and m0="1001"and s1="0101"and s0="1001"then
q1024<='1';
  else
q1024<='0';
 end if;
end if;
end process;
 end art;