mcfsqdsp3.v

一种脉冲发生器的实现

// Xilinx XPort Language Converter, Version 4.1 (110)
// 
// AHDL    Design Source: mcfsqdsp3.tdf
// Verilog Design Output: mcfsqdsp3.v
// Created 28-Nov-2007 04:17 PM
//
// Copyright (c) 2007, Xilinx, Inc.  All Rights Reserved.
// Xilinx Inc makes no warranty, expressed or implied, with respect to
// the operation and/or functionality of the converted output files.
// 

module mcfsqdsp3(clk, clr, ena, d, q, qq);
   input clk, clr, ena;
   input [15:0] d;
   output [15:0] q;
   output qq;

   wire [15:0] count;
   wire [15:0] xf;
   wire xh, xh_clk, xh_ena, vcc, xf0_clrn_ctrl, xf0_clk_ctrl, count0_clrn_ctrl,
	 count0_clk_ctrl;
   reg [15:0] count_d;
   reg [15:0] count_q;
   reg [15:0] xf_d;
   reg [15:0] xf_q;
   reg xh_d, xh_q, xh_ena_1, xh_ena_2;


   always @(posedge count0_clk_ctrl or negedge count0_clrn_ctrl)
      if (!count0_clrn_ctrl)
	 count_q <= 16'h0;
      else
	 count_q <= count_d;

   always @(posedge xf0_clk_ctrl or negedge xf0_clrn_ctrl)
      if (!xf0_clrn_ctrl)
	 xf_q <= 16'h0;
      else
	 xf_q <= xf_d;

   always @(posedge xh_clk)
      if (xh_ena)
	 xh_q <= xh_d;

// Start of original equations
   assign count0_clk_ctrl = clk;
   assign count0_clrn_ctrl = !clr;
   assign xf0_clk_ctrl = clk;
   assign xh_clk = clk;
   assign xf0_clrn_ctrl = !clr;


   always @(ena or count_q or d or xf_q) begin
      xf_d = 16'h0;
      if (ena & count_q == 16'h1) begin
	 xf_d = d;
      end else begin
	 xf_d = xf_q;
      end
   end


   always @(xf_q or vcc or ena or d or count_q) begin
      count_d = 16'b0000_0000_0000_0000;
      {xh_d, xh_ena_1} = 2'b0x;
      if (ena & count_q == xf_q & xf_q > 16'h0) begin
	 xh_d = vcc;
	 xh_ena_1 = vcc;
	 count_d = 16'h1;
      end else if (ena & d > 16'h3) begin
	 count_d = count_q + 16'h1;
      end
   end


   always @(count_q or vcc) begin
      xh_ena_2 = 1'bx;
      if (count_q == 16'h7 | count_q == 16'h6) begin
	 xh_ena_2 = vcc;
      end
   end
   assign q = count_q;
   assign qq = xh_q;


// Assignments added to explicitly combine the
// effects of multiple drivers in the source
   assign xh_ena = xh_ena_1 | xh_ena_2;

// Define power signal(s)
   assign vcc = 1'b1;
endmodule