test_sll_srl.v

来自「组成原理大作业--基于MIPS的运算器设计」· Verilog 代码 · 共 21 行

module test_sll_srl;
reg [31:0] op;
reg clock;
wire [31:0] result;
wire overflow,zero,pn;
arithmetic calca(op,clock,result,overflow,zero,pn);
always begin #25 clock=~clock;end
initial
	begin
		clock=1;
		$monitor("test arithmetic",$time,,,
		"op=%b,clock=%b,result=%b,overflow=%b,zero=%b,pn=%b",op,clock,result,overflow,zero,pn);
		#50 op='b00111100000000000001001000110100; // lui s0,1234
		#50 op='b00110100000000000101011001111000; // ori s0,s0,5678
		#50 op='b00000000000000000000000111000000; // sll s0,s0,7
		#50 op='b00111100000000000001001000110100; // lui s0,1234
		#50 op='b00110100000000000101011001111000; // ori s0,s0,5678
		#50 op='b00000000000000000000000111000010; // srl s0,s0,7
		#50 $finish;
	end
endmodule