test_div.v

来自「组成原理大作业--基于MIPS的运算器设计」· Verilog 代码 · 共 30 行

module test_div;
reg [31:0] op;
reg clock;
wire [31:0] result;
wire overflow,zero,pn;
arithmetic calca(op,clock,result,overflow,zero,pn);
always begin #25 clock=~clock;end
initial
	begin
		clock=1;
		$monitor("test arithmetic",$time,,,
		"op=%b,clock=%b,result=%b,overflow=%b,zero=%b,pn=%b",op,clock,result,overflow,zero,pn);
		#50 op='b00111100000000000000111111111111; // lui s0,0fff
		#50 op='b00110100000000000000000000000000; // ori s0,s0,000
		#50 op='b00111100001000010000000000000000; // lui s1,0000
		#50 op='b00110100001000010000111111111111; // ori s1,s1,0fff
		#50 op='b00000000000000010000100000011010; // div s1,s0,s1
		#50 op='b00111100000000000001001000110100; // lui s0,1234
		#50 op='b00110100000000000101011001111000; // ori s0,s0,5678
		#50 op='b00111100001000011111111111111111; // lui s1,ffff
		#50 op='b00110100001000011111111111111111; // ori s1,s1,ffff
		#50 op='b00000000000000010000100000011010; // div s1,s0,s1
		#50 op='b00111100000000000001001000110100; // lui s0,1234
		#50 op='b00110100000000000101011001111000; // ori s0,s0,5678
		#50 op='b00111100001000011111111111111111; // lui s1,ffff
		#50 op='b00110100001000011111111111111111; // ori s1,s1,ffff
		#50 op='b00000000000000010000100000011011; // divu s1,s0,s1
		#50 $finish;
	end
endmodule