test_arithmetic.v

组成原理大作业--基于MIPS的运算器设计

module test_arithmetic;
reg [31:0] op;
reg clock;
wire [31:0] result;
wire overflow,zero,pn;
arithmetic calca(op,clock,result,overflow,zero,pn);
always begin #25 clock=~clock;end

initial
   begin
       clock=1;
       $monitor("test arithmetic",$time,,,
       "op=%b,clock=%b,result=%b,overflow=%b,zero=%b,pn=%b",op,clock,result,overflow,zero,pn);
       #50 op=32'b00111110000100000001001000110100;   //lui s0,1234
      #50 op=32'b00110110000100000101011001111000;   //ori s0,s0,5678
      #50 op=32'b00111110001100011111111011011100;   //lui s1,s1,fedc
      #50 op=32'b00110110001100011011101010011000;   //ori s1,s1,ba98
      #50 op=32'b00000010000100011000000000100010;   //sub s0,s0,s1

      #50 op=32'b00111110000100000001001000110100;   //lui s0,s0,1234
      #50 op=32'b00110110000100000101011001111000;   //ori s0,s0,5678
      #50 op=32'b00111110001100011111111011011100;   //lui s1,s1,fedc
      #50 op=32'b00110110001100011011101010011000;   //ori s1,s1,ba98
      #50 op=32'b00000010000100011000000000100100;   //and s0,s0,s1

      #50 op=32'b00111110000100000000000000000000;   //lui s0,s0,0000
      #50 op=32'b00110110000100000001011001111000;   //ori s0,s0,1678
      #50 op=32'b00111110001100010000000000000000;   //lui s1,s1,0000
      #50 op=32'b00110110001100010011101010011000;   //ori s1,s1,3a98
      #50 op=32'b00000010000100011000000000011000;   //mult s0,s0,s1

      #50 op=32'b00111110000100000001001000110100;   //lui s0,s0,1234
      #50 op=32'b00110110000100000101011001111000;   //ori s0,s0,5678
      #50 op=32'b00111110001100010111111011011100;   //lui s1,s1,7edc
      #50 op=32'b00110110001100011011101010011000;   //ori s1,s1,ba98
      #50 op=32'b00000010000100011000000000011010;   //div s0,s0,s1

      #50 op=32'b00111110000100000001001000110100;   //lui s0,s0,1234
      #50 op=32'b00110110000100000101011001111000;   //ori s0,s0,5678
      #50 op=32'b00000000000100001000101111000000;   //sll s1,s0,15

      #50 op=32'b00111110100101000001001000110100;   //lui s4,s4,1234
      #50 op=32'b00110110100101000101011001111000;   //ori s4,s4,5678
      #50 op=32'b00100010100101011111111111111111;   //addi s5,s4,0fff
      #50 $finish;
   end
endmodule