test_sltcontrol.v

来自「组成原理大作业--基于MIPS的运算器设计」· Verilog 代码 · 共 20 行

module test_sltcontrol;
reg signslt;
reg [31:0] in;
wire [31:0] out;
integer i;
sltcontrol s1(signslt,in,out);
initial
begin
    $monitor("test of signcontrol",$time,,,
    "signslt=%b,in=%b,out=%b",signslt,in,out);
    #50 signslt=0;in='h80000000;
    for(i=0;i<=10;i=i+1)
       #50 in=in+'h0000000f;
    #50 signslt=1;in='h60000000;
    for(i=0;i<=10;i=i+1)
       #50 in=in+'h0000000f;
     
end

endmodule