test8.v

来自「组成原理大作业--基于MIPS的运算器设计」· Verilog 代码 · 共 26 行

module test8;
  reg [7:0] ina,inb,less,cin;
  reg [3:0] op;
  wire [7:0] out;
  wire cout;
  integer i;
  alu8 u1(ina,inb,op,less,cin,out,cout);
  initial
    begin
        $monitor("test",$time,,,
       "op=%b,a=%b,b=%b,result=%b,cout=%b",op,ina,inb,out,cout);
        less=8'b0;cin=0;
        #50 op='b0000;ina='b10101011;inb='b10110100;
        for(i=1;i<7;i=i+1)
        #50 inb=inb+'b00000110;
        #50 op='b0001;ina='b10101011;inb='b10110100;
        for(i=1;i<7;i=i+1)
        #50 inb=inb+'b00000110;
        #50 op='b0010;ina='b10101011;inb='b00000100;
        for(i=1;i<7;i=i+1)
        #50 inb=inb+'b00000010;
        #50 cin=1;op='b0110;ina='b10101011;inb='b00000100;
        for(i=1;i<7;i=i+1)
        #50 inb=inb+'b00000010;
    end
endmodule