test_divider32.v

来自「组成原理大作业--基于MIPS的运算器设计」· Verilog 代码 · 共 17 行

module test_divider32;
    reg [31:0] a,b;
    wire [31:0] out,r;
    integer i;
    wire zero;
    divider32 u1(a,b,out,r,zero);
    initial 
    begin 
       $monitor("test of divider32",$time,,,
       "a=%h,b=%h,out=%h,r=%b，zero=%b",a,b,out,r,zero);
        a='h0000bbbb;b='h00000007;
       #50 a='h99999999;b='h99999999;
       for(i=1;i<10;i=i+1)
        #50 b=b<<1;
    end
   endmodule