test_alucontrl.v

组成原理大作业--基于MIPS的运算器设计

module test_alucontrl;

reg [31:0] op;
wire [1:0]  aluOp , outcalc;
wire ina , inb , writein , shiftsign, extend , luisign , sign , signslt;
wire [3:0] aluCtrl ;

alucontrl u1( op , ina , inb , aluOp , aluCtrl , writein , outcalc , shiftsign , extend , luisign , sign , signslt);
initial
   begin
   $monitor("test of control",$time,,,
   "op=%b,ina=%b,inb=%b,aluOp=%b,aluCtrl=%b,writein=%b,outcalc=%b,shiftsign=%b,extend=%b,luisign=%b,sign=%b,signslt=%b",op,ina,inb,aluOp,aluCtrl,writein,outcalc,shiftsign,extend,luisign,sign,signslt);
	#50 op=32'b00000010000100001010000000100000;		//add
	#50 op=32'b00000010000100001010000000100001;		//addu
	#50 op=32'b00000010000100001010000000100010;		//sub
	#50 op=32'b00000010000100001010000000100011;		//subu
	#50 op=32'b00000010000100001010000000100100;		//and
	#50 op=32'b00000010000100001010000000100101;		//or
	#50 op=32'b00000010000100001010000000100110;		//xor
	#50 op=32'b00000010000100001010000000100111;		//nor
	#50 op=32'b00000010000100001010000000000000;		//sll
	#50 op=32'b00000010000100001010000000000010;		//slr
	#50 op=32'b00000010000100001010000000011000;		//mult
	#50 op=32'b00000010000100001010000000011001;		//multu
	#50 op=32'b00000010000100001010000000101010;		//slt 
	#50 op=32'b00000010000100001010000000101011;		//sltu
	#50 op=32'b00000010000100001010000000011010;		//div
	#50 op=32'b00000010000100001010000000011011;		//divu
	#50 op=32'b00100000000000011111111111111111;		//addi	
	#50 op=32'b00100110000100001010000000100001;		//addiu
	#50 op=32'b00101010000100001010000000100001;		//slti
	#50 op=32'b00101110000100001010000000100001;		//sltiu
	#50 op=32'b00110010000100001010000000100001;		//andi
	#50 op=32'b00110110000100001010000000100001;		//ori
	#50 op=32'b00111010000100001010000000100001;		//xori
	#50 op=32'b00111110000100001010000000100001;		//lui
	#50 $finish;
   end
endmodule