test_reg.v

来自「组成原理大作业--基于MIPS的运算器设计」· Verilog 代码 · 共 25 行

module test_reg;
    reg regwrite,clock;
    reg [4:0] read1,read2,writereg;  
    reg [31:0] writedata;
    wire [31:0] data1,data2;
    integer i;
    registerfile u1(read1,read2,writereg,writedata,regwrite,data1,data2,clock);
    always 
       begin #50 clock=~clock;end
    initial
       begin
           $monitor("test of register",$time,,,
           "regwrite=%b,writereg=%h,writedata=%h,read1=%h,readdata1=%h,read2=%h,readdata2=%h",regwrite,writereg,writedata,read1,data1,read2,data2);
           clock=0;
           for(i=0;i<32;i=i+1)
              begin
              #100 regwrite=1;writereg=i;writedata=i;
              end
           for(i=0;i<32;i=i+2)
              begin
              #100 regwrite=0;read1=i;read2=i+1;
              end
           #4800 $finish;
       end
endmodule