test_shift.v

来自「组成原理大作业--基于MIPS的运算器设计」· Verilog 代码 · 共 19 行

`timescale 1ps/1ps
module test_shift;
reg ena,clk,shifttype;
reg [4:0] shamt;
reg [31:0] setvalue;
wire [31:0] result;
shift u1(ena,clk,setvalue,shifttype,shamt,result);
always 
    begin #50 clk=~clk;end
initial
    begin
        $monitor("test_shift",$time,,,
        "setvalue=%b,shifttype=%b,shamt=%b,result=%b",setvalue,shifttype,shamt,result);
        clk=0;
       #50 ena=1;setvalue='habcdef12;shifttype=0;shamt=10;
       #3300 $finish;
   end
   endmodule