test_mult32.v

来自「组成原理大作业--基于MIPS的运算器设计」· Verilog 代码 · 共 15 行

module test_mult32;
    reg [31:0] ina,inb;
    wire [31:0] out;
    wire overflow,zero;
    integer i;
    mult32 u1(ina,inb,out,overflow,zero);
    initial
       begin
           $monitor("test",$time,,,
           "ina=%h,inb=%h,out=%h,overflow=%b,zero=%b",ina,inb,out,overflow,zero);
           ina='h0000bbbb;inb='h00000007;
           for(i=1;i<14;i=i+1)
           #50 inb=inb<<1;
       end
   endmodule