test_bitext.v

来自「组成原理大作业--基于MIPS的运算器设计」· Verilog 代码 · 共 22 行

module test_bitext;
reg ena,flag,sign;
reg [15:0] in;
wire [31:0] out;
bitext u1(ena,in,flag,sign,out);
initial
begin
    $monitor("test_bitext",$time,,,
    "flag=%b,in=%b,out=%b",flag,in,out);
    ena=1;flag=1;sign=1;
    #50 in='h1234;
    #50 in='h5678;
    #50 in='h9abc;
    #50 in='hdef0;
    #50 in='hffff;
    #50 flag=0;in='h1234;
    #50 in='h5678;
    #50 in='h9abc;
    #50 in='hdef0;
    #50 in='hffff;
end
endmodule