test_alu.v

来自「组成原理大作业--基于MIPS的运算器设计」· Verilog 代码 · 共 30 行

module test_alu;
    reg[31:0] ina,inb;
    reg[3:0] op;
    wire[31:0] out;
    wire cout,overflow,zero;
    integer i;
    alu32 u1(ina,inb,op,out,cout,overflow,zero);
    always 
     begin
         $monitor("ALU test",$time,,,
         "op=%b,a=%h,b=%h,result=%h,cout=%b,overflow=%b,zero=%b",op,ina,inb,out,cout,overflow,zero);
        #50 op='b0000;ina='hbbbbbbbb;inb='h66666666;
        for(i=1;i<7;i=i+1)
         #50 inb=inb+'h0000000f;
        #50 op='b0001;ina='hbbbbbbbb;inb='h66666666;
        for(i=1;i<7;i=i+1)
         #50 inb=inb+'h0000000f; 
        #50 op='b0010;ina='h00000000;inb='h10101010;
        for(i=1;i<7;i=i+1)
         #50 ina=ina+'h0000000f;
        #50 op='b0010;ina='hbbbbbbbb;inb='h66666666;
        #50 op='b0110;ina='h10000001;inb='h00000011;
        for(i=1;i<7;i=i+1)
         #50 inb=inb+'h0000000f; 
        #50 op='b0111;ina='h10000001;inb='h00000011;
        #50 op='b0111;ina='h10000001;inb='h10000001;
        #50 op='b0111;ina='h10000001;inb='h10000011;
        #50 $finish;
     end 
endmodule