cntrlunit.v

turbo码_verilog_编码源文件

/*	-------------------------------------------------------------------------
Author:QiuPing Zhong
Date:Oct 18th,2004
Veision: 

Function:complete interleaver
CLK:
DataIn_Speed:clk
DataOut_Speed:clk
Delay:
-----------------------------------------------------------------------------*/
module cntrlunit(//input:
                 data_clk,
					  reset_n,   //global
					  framehead, //related to upper class module;
					  //output:
					  addrw,	//related to delay_ram and inter_ram
					  wen, //related to delay_ram and inter_ram
					  interaddr_addrr,//related to interaddr_ram
					  delay_addrr,//related to delay_ram
					  inter_addrr_h,//related to inter_ram
					  interleaver_over,//relatedd to the fflowed module
					  //for test
					//	wcnt4096,
                 // wcnt2,
                 // rcnt4096,
                  //rcnt2,
						//interaddr_rd_start_en,
						tailinen
					  );


input data_clk;
input reset_n;
input framehead;
output [13:0] addrw;
output wen;
output [11:0] interaddr_addrr;
output [13:0] delay_addrr;
output inter_addrr_h;
output interleaver_over;
output tailinen;
//for test

//output [12:0] wcnt4096;
//output wcnt2;
//output [12:0] rcnt4096;
//output rcnt2;
//output interaddr_rd_start_en;

reg [12:0] wcnt4096;
reg wcnt2;
reg [12:0] rcnt4096;
reg rcnt2;

wire [13:0] addrw;
wire wen;
wire interaddr_rd_start_en;
wire [11:0] interaddr_addrr;
reg [13:0] delay_addrr;
reg inter_addrr_h;
reg interleaver_over;
reg tailinen;
//the following code generate:
//1: the addrw and addrr for Part 1: delay_ram
//2: the addrw and addrr(from the interaddr_ram) for Part 2: inter_ram
//3: the addrr for part3:interaddr_ram

// the counter for writing
//Part 1 and Part 2 's addrw is the same,so use the same counter and addrw and wen
always@(posedge data_clk or posedge reset_n)
begin 
  if(reset_n)
    wcnt4096<=13'd4096;
  else if(framehead)
       wcnt4096<=0;
		 else if(!wcnt4096[12])
		      wcnt4096<=wcnt4096+1;
end

//wcnt2 indicating even or odd frame,then according wcnt2 change the addrw
always@(posedge data_clk or posedge reset_n)
begin 
  if(reset_n)
    wcnt2<=1'b1;
  else if(framehead)
          wcnt2<=wcnt2+1;
end

//generate delay_addrw  and inter_addrw,they are the same
assign addrw=(reset_n)?0:{1'b0,wcnt2,wcnt4096[11:0]};

//generate write enable,when wen=1,write effctive,wen=1,write ineffective
//delay_wen and inter_wen are the same
assign wen=!wcnt4096[12];

//generate the read start enable signal,when wcnt4096=4094;
assign interaddr_rd_start_en=(&wcnt4096[11:1])&&(!wcnt4096[0]);

//counter for reading,counter is effective at wcnt4096=4095; 
always@(posedge data_clk or posedge reset_n)
begin 
  if(reset_n)
    rcnt4096<=13'd4096;
  else if(interaddr_rd_start_en)
       rcnt4096<=0;
		 else if(!rcnt4096[12])
		      rcnt4096<=rcnt4096+1;
end

//generate interaddr_addrr;
//interaddr_addrr is 1 data_clk ahead of delay_addrr
//interaddr_addrr is effective at wcnt4096=4095
assign interaddr_addrr=(reset_n)?0:{rcnt4096[11:0]};

//rcnt2 indicating even or odd frame,then according rcnt2 change the addrr
always@(posedge data_clk or posedge reset_n)
begin 
  if(reset_n)
     rcnt2<=1'b1;
  else if(interaddr_rd_start_en)
          rcnt2<=rcnt2+1;
end

//generate delay_addrr is 1 clk after interaddr_addrr
//delay_addrr is effective at wcnt4096=4096,means 0;
always@(posedge data_clk or posedge reset_n)
begin 
  if(reset_n)
     	delay_addrr<=14'd0;
  else  
      delay_addrr<={1'b0,rcnt2,rcnt4096[11:0]};
end

//generate the hign bit for inter_addrr
always@(posedge data_clk or posedge reset_n)
begin 
  if(reset_n)
     	inter_addrr_h<=0;
  else  
      inter_addrr_h<=rcnt2;
end

//genertate the interleaver over signal
always@(posedge data_clk or posedge reset_n)
begin 
  if(reset_n)
     interleaver_over<=0;
  else if(&(wcnt4096[11:0]))
         interleaver_over<=1;
       else 
		   interleaver_over<=0;
end

//genrerate the tailen  fot the interbit and bit 
always@(posedge data_clk or posedge reset_n)
begin 
  if(reset_n)
     tailinen<=0;
  else if(rcnt4096==13'd4092)
         tailinen<=1;
       else 
		   tailinen<=0;
end
endmodule