interaddr_ram.v

来自「turbo码_verilog_编码源文件」· Verilog 代码 · 共 51 行

module interaddr_ram(//input:
                     data_clk,//global
                     interaddr_addrr,//related to cntrlunit module
							//output:
							inter_addrr);


input data_clk;
input [11:0] interaddr_addrr;
output [11:0] inter_addrr; 

wire [11:0] interaddr_addrr;
wire [11:0] inter_addrr;  
 
/* the following three RAM is holding the address for interleaver with ucf file,
   they are only read,and the three RAM have the same read address, 
	the outputs of the three RAM with one address consist of one address for interlever*/  

RAMB16_S4 inter_addr0(.DO(inter_addrr[3:0]),  //[3:0] DO;
           .ADDR(interaddr_addrr), //[11:0] ADDR;
           .DI(), //[3:0] DI;
           .EN(1'b1), 
           .CLK(data_clk), 
           .WE(1'b0), 
           .SSR(1'b0)
			  );


RAMB16_S4 inter_addr1(.DO(inter_addrr[7:4]),  //[3:0] DO;
           .ADDR(interaddr_addrr), //[11:0] ADDR;
           .DI(), //[3:0] DI;
           .EN(1'b1), 
           .CLK(data_clk), 
           .WE(1'b0), 
           .SSR(1'b0)
			  );


RAMB16_S4 inter_addr2(.DO(inter_addrr[11:8]),  //[3:0] DO;
           .ADDR(interaddr_addrr), //[11:0] ADDR;
           .DI(), //[3:0] DI;
           .EN(1'b1), 
           .CLK(data_clk), 
           .WE(1'b0), 
           .SSR(1'b0)
			  );



endmodule