turboencoder.v

turbo码_verilog_编码源文件

module turboencoder(//input:
                    reset_n,
                    data_clk,
                    framehead,
                    bitin,
						  //output:
                    syscodeout,
                    paricodeout,
                    turboencoder_over
						  //for test:
						  //interbitout,
                    //interleaver_over,
                    //sysbitout1,
                    //paribitout1,
                    //sysbitout2,
                    //paribitout2,
                    //rscencoder_over,
                    //tailouten
						  );
    input reset_n;
    input data_clk;
    input framehead;
    input bitin;
    output syscodeout;
    output paricodeout;
    output turboencoder_over;

//output  interbitout;
//output  interleaver_over;
//output  sysbitout1;
//output paribitout1;
//output sysbitout2;
//output paribitout2;
//output rscencoder_over;
//output tailouten;

 wire  bitout;
 wire  interbitout;
 wire  interleaver_over;
 wire  sysbitout1;
 wire paribitout1;
 wire sysbitout2;
 wire paribitout2;
 wire rscencoder_over;
 wire tailouten;
 wire turboencoder_over;
 wire tailinen;

interleaver turboencoder_uut0 (
    .data_clk(data_clk), 
    .reset_n(reset_n), 
    .bitin(bitin), 
    .framehead(framehead), 
    .bitout(bitout), 
    .interbitout(interbitout), 
    .interleaver_over(interleaver_over),
	 .tailinen(tailinen)
    );

RSC_7_5encoder turboencoder_uut1 (
    .data_clk(data_clk), 
    .reset_n(reset_n), 
    .framehead(interleaver_over), 
    .bitin(bitout),
	 .tailinen(tailinen), 
    .sysbitout(sysbitout1), 
    .paribitout(paribitout1), 
    .rscencoder_over(rscencoder_over), 
    .tailouten(tailouten)
    );

interRSC_7_5encoder turboencoder_uut2 (
    .data_clk(data_clk), 
    .reset_n(reset_n), 
    .framehead(interleaver_over), 
    .bitin(interbitout),
	 .tailinen(tailinen), 
    .sysbitout(sysbitout2), 
    .paribitout(paribitout2)
    );

puncture turboencoder_uut3 (
    .reset_n(reset_n), 
    .data_clk(data_clk), 
    .framehead(rscencoder_over), 
    .tailinen(tailouten), 
    .sysbitin1(sysbitout1), 
    .paribitin1(paribitout1), 
    .sysbitin2(sysbitout2), 
    .paribitin2(paribitout2), 
    .syscodeout(syscodeout), 
    .paricodeout(paricodeout), 
    .turboencoder_over(turboencoder_over)
    );



endmodule