turbo_encoder.npl

turbo码_verilog_编码源文件

JDF F
// Created by Project Navigator ver 1.0
PROJECT turbo_encoder
DESIGN turbo_encoder Normal
DEVFAM virtex2
DEVFAMTIME 0
DEVICE xc2v3000
DEVICETIME 0
DEVPKG ff1152
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
FLOW Synplify Pro Verilog
FLOWTIME 0
STIMULUS interRSC_7_5encodertest.tf Normal
STIMULUS puncturetest.tf Normal
STIMULUS RSC_7_5encoderteset.tf Normal
STIMULUS turboencodertest.tf Normal
STIMULUS interaddrram_test.tf Normal
STIMULUS interleavertest.tf Normal
STIMULUS cntrlunittest.tf Normal
MODULE interRSC_7_5encoder.v
MODSTYLE interRSC_7_5encoder Normal
MODULE interleaver.v
MODSTYLE interleaver Normal
MODULE cntrlunit.v
MODSTYLE cntrlunit Normal
MODULE delay_ram.v
MODSTYLE delay_ram Normal
MODULE inter_ram.v
MODSTYLE inter_ram Normal
MODULE puncture.v
MODSTYLE puncture Normal
MODULE turboencoder.v
MODSTYLE turboencoder Normal
MODULE interaddr_ram.v
MODSTYLE interaddr_ram Normal
MODULE RSC_7_5encoder.v
MODSTYLE RSC_7_5encoder Normal
DEPASSOC turboencoder interaddrTab.ucf Normal
DEPASSOC interleaver interleaveraddr.ucf Normal
DEPASSOC interaddr_ram interaddr.ucf Normal
[Normal]
p_ModelSimSignalWin=synprovlg, virtex2, Module Test Fixture.t_MSimulatePostPlace&RouteVerilogModel, 1102488852, False
p_ModelSimSimRunTime_tb=synprovlg, virtex2, Module Test Fixture.t_MSimulatePostPlace&RouteVerilogModel, 1102488852, -all
p_ModelSimStructWin=synprovlg, virtex2, Module Test Fixture.t_MSimulatePostPlace&RouteVerilogModel, 1102488852, False
[STATUS-ALL]
interleaver.postParVerilogSimModel=WARNINGS,1105323284
interRSC_7_5encoder.postParVerilogSimModel=WARNINGS,1105323284
turboencoder.postParVerilogSimModel=WARNINGS,1105323284
[STRATEGY-LIST]
Normal=True