puncture.v

turbo码_verilog_编码源文件

/*	-------------------------------------------------------------------------
Author:QiuPing Zhong
Date:Oct 18th,2004
Veision: 

Function:complete puncture
CLK: 1 data_clk
DataIn_Speed:
DataOut_Speed:
delay: 1 clk
---------------------------------------------------------------------------*/
module puncture(//input:
                reset_n,
                data_clk,
					 framehead,
                tailinen,
                sysbitin1,
                paribitin1,
                sysbitin2,
					 paribitin2,
					 //output:
					 syscodeout,
					 paricodeout,
					 turboencoder_over
					 //test:
					 //cnt2,
					 //cnt4,
					 //sysbitin2_d,
					 //sysbitin2_dd,
					 //paribitin2_d,
					 //paribitin2_dd
					 );
  
 input   reset_n;
 input   data_clk;
 input   framehead;
 input   tailinen;
 input   sysbitin1;
 input   paribitin1;
 input   sysbitin2;
 input   paribitin2;
 output	syscodeout;
 output	paricodeout;
 output	turboencoder_over; 

//output  cnt2;
//output [2:0] cnt4;
//output sysbitin2_d;
//output sysbitin2_dd;
//output paribitin2_d;
//output paribitin2_dd;
																		 
reg  cnt2;
reg [2:0] cnt4;

reg sysbitin2_d;
reg sysbitin2_dd;

reg paribitin2_d;
reg paribitin2_dd;

reg syscodeout;
reg paricodeout;

reg turboencoder_over;


/*the function of cnt2 is to indicate the even or odd bits*/
always@(posedge data_clk or posedge reset_n)
begin
if(reset_n)
 cnt2<=1'd0;
 else if(framehead)//framehead stands for effective of rsc
         cnt2<=1'd0;
		else   
		   cnt2<=cnt2+1;  
end



/*the function of cnt4 is to process tailbits*/
always@(posedge data_clk)
begin
if(reset_n)
 cnt4<=3'd4;
 else if(tailinen)//TailbitOutEn1 stands for effective of tailer
        cnt4<=0;
		else if(!cnt4[2])
		  cnt4<=cnt4+1;
end



/*Brief:	
as we know,each frame contain 4096 bits.
for the sysbit frame, the first 4092 bits come from RSC1,
     the 4093 to 4094 bits also come from RSC1,
	  but the 4095 to 4096 bits come from the 4093 to 4094 bits of RSC2.
for the paribit frame, the first 4092 bits come from RSC1 and RSC2 ,
	  with RSC1 contributs its even bits,and RSC1 odd bits;
	  the 4093 to 4094 bits a come from  the 4093 to 4094 bits of RSC1,
	  the 4095 to 4096 bits come from the 4093 to 4094 bits of RSC2.
*/


//delay 2 data_clk
always@(posedge data_clk or posedge reset_n)
begin
   if(reset_n)
	  begin
	  sysbitin2_d<=0;
	  sysbitin2_dd<=0;
	  end
   else 
	  begin
	  sysbitin2_d<=sysbitin2;
	  sysbitin2_dd<=sysbitin2_d;
	  end
end

//delay 2 data_clk
always@(posedge data_clk or posedge reset_n)
begin
   if(reset_n)
	  begin
	  paribitin2_d<=0;
	  paribitin2_dd<=0;
	  end
   else 
	  begin
	  paribitin2_d<=paribitin2;
	  paribitin2_dd<=paribitin2_d;
	  end
end

always@(posedge data_clk or posedge reset_n)
begin
   if(reset_n)
	syscodeout<=0;
	else if(!cnt4[2])
	        begin
			    if(!cnt4[1])
				    syscodeout<=sysbitin1; 
				 else 
				    syscodeout<=sysbitin2_dd;  
	     	  end
        else
		     syscodeout<=sysbitin1;
end

always@(posedge data_clk or posedge reset_n)
begin
   if(reset_n)
	paricodeout<=0;
	else if(!cnt4[2])
	        begin
			    if(!cnt4[1])
				    paricodeout<=paribitin1; 
				 else 
				    paricodeout<=paribitin2_dd;  
	     	  end
        else
		     begin
			    if(!cnt2)
				    paricodeout<=paribitin1; 
				 else 
				    paricodeout<=paribitin2;  
	     	  end
end

always@(posedge data_clk or posedge reset_n)
begin
   if(reset_n)
	  turboencoder_over<=0;
   else
	  turboencoder_over<=framehead;
end

endmodule