inter_ram.v

turbo码_verilog_编码源文件

module inter_ram(//input:
                  reset_n,
                  data_clk,
						bitin,
						addrw,//related to cntrlunit 
						wen, //related to cntrlunit 
						inter_addrr_h,//related cntrlunit
						inter_addrr,//related to interaddr_ram
						//output:
						interbitout);
input reset_n; 
input data_clk;
input bitin;
input [13:0] addrw;
input wen;
input inter_addrr_h;
input [11:0] inter_addrr;

output interbitout; 


wire [13:0] addrw;
wire wen;
wire inter_addrr_h;
wire [11:0] inter_addrr; 
wire [13:0] interaddrr;

wire interbitout;

assign interaddrr=(reset_n)?0:{1'b0,inter_addrr_h,inter_addrr};


/*the purpose of inter_out RAM is make the interbit out by the read address*/
RAMB16_S1_S1 inter_out(.DOA(),//[0:0] DOA; 
              .DOB(interbitout), //[0:0] DOB;
              .ADDRA(addrw),//[13:0] ADDRA; 
              .CLKA(data_clk), 
              .DIA(bitin), //[0:0] DIA; 
              .ENA(wen), 
              .SSRA(1'b0), 
              .WEA(1'b1), 
              .ADDRB(interaddrr),//[13:0] ADDRB; 
              .CLKB(data_clk), 
              .DIB(),//[0:0] DIB;
              .ENB(1'b1), 
              .SSRB(1'b0), 
              .WEB(1'b0)
				 );



endmodule