interleaver.v

turbo码_verilog_编码源文件

/*	-------------------------------------------------------------------------
Author:QiuPing Zhong
Date:Oct 18th,2004
Veision: 

Function:complete interleaver
CLK:
DataIn_Speed:clk
DataOut_Speed:clk
Delay: 4097 clk
---------------------------------------------------------------------------*/
module interleaver( //input:
                    data_clk,
						  reset_n,	//global
						  framehead,//related upper class
						  bitin,	//related to upper class
						  //output:
						  bitout,//related to Rscencoder
						  interbitout,//related to Rscencoder
						  interleaver_over,
						  tailinen
						  //test
						  //addrw,
						  //wen,
						  //interaddr_addrr,
						  //delay_addrr,
						  //inter_addrr_h,
						  //inter_addrr
                      );
    
	 
input data_clk;
input reset_n;
input bitin;
input framehead;
output bitout;
output interbitout;
output interleaver_over;
output tailinen;
//for test
//output [13:0] addrw;
//output wen;
//output [11:0] interaddr_addrr;
//output [13:0] delay_addrr;
//output inter_addrr_h;
//output [11:0] inter_addrr; 

wire framehead;
wire bitin;
wire [13:0] addrw;
wire wen;
wire [11:0] interaddr_addrr;
wire [13:0] delay_addrr;
wire inter_addrr_h;
wire [11:0] inter_addrr; 
wire interleaver_over;
wire bitout;
wire interbitout;

    
cntrlunit interleaver_uut0 (
    .data_clk(data_clk), 
    .reset_n(reset_n), 
    .framehead(framehead), 
    .addrw(addrw), 
    .wen(wen), 
    .interaddr_addrr(interaddr_addrr), 
    .delay_addrr(delay_addrr), 
    .inter_addrr_h(inter_addrr_h), 
    .interleaver_over(interleaver_over),
	 .tailinen(tailinen)
    );


delay_ram interleaver_uut1 (
   
    .data_clk(data_clk), 
    .bitin(bitin), 
    .addrw(addrw), 
    .wen(wen), 
    .delay_addrr(delay_addrr), 
    .bitout(bitout)
    );

interaddr_ram interleaver_uut2 (
    .data_clk(data_clk), 
    .interaddr_addrr(interaddr_addrr), 
    .inter_addrr(inter_addrr)
    );

inter_ram interleaver_uut3 (
    .reset_n(reset_n),
    .data_clk(data_clk), 
    .bitin(bitin), 
    .addrw(addrw), 
    .wen(wen), 
    .inter_addrr_h(inter_addrr_h), 
    .inter_addrr(inter_addrr), 
    .interbitout(interbitout)
    );

endmodule