test1.rpt

各种VHDL的开发资料

  76    120    H     OUTPUT      t        0      0   0    3    0    0    0  D4
  81    128    H     OUTPUT      t        0      0   0    3    0    0    0  D5
  80    126    H     OUTPUT      t        0      0   0    3    0    0    0  D6
  79    125    H     OUTPUT      t        0      0   0    3    0    0    0  D7


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                 c:\edatest\altera\test1\test1.rpt
test1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                         Logic cells placed in LAB 'H'
        +--------------- LC123 D0
        | +------------- LC115 D1
        | | +----------- LC117 D2
        | | | +--------- LC118 D3
        | | | | +------- LC120 D4
        | | | | | +----- LC128 D5
        | | | | | | +--- LC126 D6
        | | | | | | | +- LC125 D7
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':

Pin
12   -> * * * * * * * * | - - - - - - - * | <-- A
11   -> * * * * * * * * | - - - - - - - * | <-- B
10   -> * * * * * * * * | - - - - - - - * | <-- C


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                 c:\edatest\altera\test1\test1.rpt
test1

** EQUATIONS **

A        : INPUT;
B        : INPUT;
C        : INPUT;

-- Node name is 'D0' 
-- Equation name is 'D0', location is LC123, type is output.
 D0      = LCELL( _EQ001 $  GND);
  _EQ001 = !A & !B & !C;

-- Node name is 'D1' 
-- Equation name is 'D1', location is LC115, type is output.
 D1      = LCELL( _EQ002 $  GND);
  _EQ002 =  A & !B & !C;

-- Node name is 'D2' 
-- Equation name is 'D2', location is LC117, type is output.
 D2      = LCELL( _EQ003 $  GND);
  _EQ003 = !A &  B & !C;

-- Node name is 'D3' 
-- Equation name is 'D3', location is LC118, type is output.
 D3      = LCELL( _EQ004 $  GND);
  _EQ004 =  A &  B & !C;

-- Node name is 'D4' 
-- Equation name is 'D4', location is LC120, type is output.
 D4      = LCELL( _EQ005 $  GND);
  _EQ005 = !A & !B &  C;

-- Node name is 'D5' 
-- Equation name is 'D5', location is LC128, type is output.
 D5      = LCELL( _EQ006 $  GND);
  _EQ006 =  A & !B &  C;

-- Node name is 'D6' 
-- Equation name is 'D6', location is LC126, type is output.
 D6      = LCELL( _EQ007 $  GND);
  _EQ007 = !A &  B &  C;

-- Node name is 'D7' 
-- Equation name is 'D7', location is LC125, type is output.
 D7      = LCELL( _EQ008 $  GND);
  _EQ008 =  A &  B &  C;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                          c:\edatest\altera\test1\test1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:07
   --------------------------             --------
   Total Time                             00:00:08


Memory Allocated
-----------------

Peak memory allocated during compilation  = 6,460K