📄 t3.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\edatest\altera\test3\t3.rpt
t3
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 2/ 96( 2%) 4/ 48( 8%) 0/ 48( 0%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\edatest\altera\test3\t3.rpt
t3
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 CLK
Device-Specific Information: c:\edatest\altera\test3\t3.rpt
t3
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 6 Rd
Device-Specific Information: c:\edatest\altera\test3\t3.rpt
t3
** EQUATIONS **
CLK : INPUT;
D : INPUT;
J : INPUT;
K : INPUT;
R : INPUT;
Rd : INPUT;
S : INPUT;
Sd : INPUT;
-- Node name is 'NQD'
-- Equation name is 'NQD', type is output
NQD = !_LC1_A2;
-- Node name is 'NQJK'
-- Equation name is 'NQJK', type is output
NQJK = !_LC5_A3;
-- Node name is 'NQRS'
-- Equation name is 'NQRS', type is output
NQRS = _LC6_B1;
-- Node name is 'NQRSC'
-- Equation name is 'NQRSC', type is output
NQRSC = _LC2_B1;
-- Node name is 'QD'
-- Equation name is 'QD', type is output
QD = _LC6_A2;
-- Node name is 'QJK'
-- Equation name is 'QJK', type is output
QJK = _LC2_A2;
-- Node name is 'QRS'
-- Equation name is 'QRS', type is output
QRS = _LC8_B1;
-- Node name is 'QRSC'
-- Equation name is 'QRSC', type is output
QRSC = _LC4_B1;
-- Node name is ':12'
-- Equation name is '_LC8_B1', type is buried
_LC8_B1 = LCELL( _EQ001);
_EQ001 = !_LC6_B1
# !Sd;
-- Node name is ':13'
-- Equation name is '_LC6_B1', type is buried
!_LC6_B1 = _LC6_B1~NOT;
_LC6_B1~NOT = LCELL( _EQ002);
_EQ002 = _LC8_B1 & Rd;
-- Node name is ':16'
-- Equation name is '_LC4_B1', type is buried
!_LC4_B1 = _LC4_B1~NOT;
_LC4_B1~NOT = LCELL( _EQ003);
_EQ003 = !CLK & _LC2_B1 & Sd
# _LC2_B1 & !S & Sd;
-- Node name is ':17'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = LCELL( _EQ004);
_EQ004 = !_LC4_B1
# !Rd
# CLK & R;
-- Node name is '~18~1'
-- Equation name is '~18~1', location is LC5_A3, type is buried.
-- synthesized logic cell
_LC5_A3 = DFFE( _EQ005, GLOBAL( CLK), GLOBAL( Rd), GLOBAL( Sd), VCC);
_EQ005 = !K & _LC5_A3
# J & !_LC5_A3;
-- Node name is ':18'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = DFFE( _EQ006, GLOBAL( CLK), GLOBAL( Rd), GLOBAL( Sd), VCC);
_EQ006 = !K & _LC2_A2
# J & !_LC2_A2;
-- Node name is '~19~1'
-- Equation name is '~19~1', location is LC1_A2, type is buried.
-- synthesized logic cell
_LC1_A2 = DFFE( D, GLOBAL( CLK), GLOBAL( Rd), GLOBAL( Sd), VCC);
-- Node name is ':19'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = DFFE( D, GLOBAL( CLK), GLOBAL( Rd), GLOBAL( Sd), VCC);
Project Information c:\edatest\altera\test3\t3.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,296K
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