msp430x42x0_clks_01.s43

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;******************************************************************************
;   MSP430x42x0 Demo - FLL+, Output MCLK, ACLK Using 32kHz XTAL and DCO
;
;   Description: This program outputs buffered MCLK and ACLK on port pins
;   P1.1 and P1.5.
;   ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
;   //* An external watch crystal between XIN & XOUT is required for ACLK *//	
;
;                 MSP430F4270
;             -----------------
;         /|\|              XIN|-
;          | |                 | 32kHz
;          --|RST          XOUT|-
;            |                 |
;            |        P1.1/MCLK|-->MCLK = 1048576Hz
;            |        P1.5/ACLK|-->ACLK = 32768Hz
;
;  L. Westlund / S. Karthikeyan
;  Texas Instruments Inc.
;  June 2005
;  Built with IAR Embedded Workbench Version: 3.30A
;******************************************************************************
#include  <msp430x42x0.h>
;------------------------------------------------------------------------------
            ORG     08000h                  ; Program Start
;------------------------------------------------------------------------------
RESET       mov.w   #300h,SP                ; Initialize stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
SetupFLL    bis.b   #XCAP14PF,&FLL_CTL0     ; Configure load caps
SetupP1     bis.b   #022h,&P1DIR            ; P1.1 and P1.5 output direction
            bis.b   #022h,&P1SEL            ; P1.1 and P1.5 option select
                                            ;				          							
Mainloop    jmp     Mainloop                ;
                                            ;
;-----------------------------------------------------------------------------
;           Interrupt Vectors
;-----------------------------------------------------------------------------
            ORG     0FFFEh                  ; RESET Vector
            DW      RESET                   ;
            END