fft说明.txt

介绍了基于FPGA的FFT实现方法

CF FFT: Overview 

Details
Name: cf_fft
Created: 05-Jan-2003 17:34:51
Updated: 08-May-2008 08:29:29
CVS: no files in cvs

Other project properties

Category :: Arithmetic core
Development status :: Production/Stable

 Project maintainers 

Tom Hawkins
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Description 

Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent for more info.

The Fast Fourier Transform converts time or spacial information into the frequency domain and is one of the most popular DSP algorithms.


Features 

The FFT architecture is pipelined on a rank basis; each rank has 
its own butterfly and ranks are isolated from each other using 
memory interleavers. This FFT can perform calculations on 
continuous streaming data (one data set right after another). 
More over, inputs and outputs are passed in pairs, doubling the 
bandwidth. For instance, a 4096 point FFT can perform a transform 
every 2048 cycles.

Each file is stand-alone and represents a specific configuration. 
The 2 parameters are: 


Number of Points 
Component (Real/Imag) Precision 
All designs are pipelined with a synchronous enable and reset.
The configuration parameters are coded in the file names: cf_fft_4096_18.v 


4K point FFT. 
18 bit precision, real and imaginary. Total is 36 bits. 
Current configurations: 

cf_fft_256_8 
cf_fft_512_8 
cf_fft_1024_8 
cf_fft_2048_8 
cf_fft_4096_8 
cf_fft_256_16 
cf_fft_512_16 
cf_fft_1024_16 
cf_fft_2048_16 
cf_fft_4096_16 
cf_fft_256_18 
cf_fft_512_18 
cf_fft_1024_18 
cf_fft_2048_18 
cf_fft_4096_18