drive.vhd

<CPLDFPGA嵌入式应用开发技术白金手册>配套源代码

--dirve
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;


entity drive is
  port(din:in std_logic_vector(3 downto 0);
       dout:out std_logic_vector(6 downto 0));
end drive;
architecture rtl of drive is
begin
 process(din)
  begin
   case din is
     when "0000"=>dout<="1000000";
     when "0001"=>dout<="1111001";
     when "0010"=>dout<="0100100";
     when "0011"=>dout<="0110000";
     when "0100"=>dout<="0011001";
     when "0101"=>dout<="0010010";
     when "0110"=>dout<="0000010";
     when "0111"=>dout<="1111000";
     when "1000"=>dout<="0000000";
     when "1001"=>dout<="0010000";
     when others=>dout<="0001000";
end case;
end process;
end rtl;