first.vhd

<CPLDFPGA嵌入式应用开发技术白金手册>配套源代码

library ieee;
use ieee.std_logic_1164.all;
entity first is
     port(a,b,c,zin,yin:in std_logic;
          dout,eout,fout,gout:out std_logic);
end first;
architecture rtl of first is
begin
   process(a,b,c,zin,yin)
     begin
	if(a='1' and b='0')then
	dout<='1';
	eout<=zin;
	fout<='0';
	gout<='0';
	elsif(a='0' and b='0')then
	dout<='0';
	eout<=yin;
	fout<='1';
	gout<='0';
	elsif(c='1')then
	dout<='1';
	eout<=zin;
	fout<='1';
	gout<='1';
	else
	dout<='1';
	eout<=zin;
	fout<='1';
 	gout<='0';
     end if;
   end process;
end rtl;