prev_cmp_multiplier.tan.qmsg

乘法器 所占资源很少 很好的一个乘法器 史书上的一个例子 说得很好啊

{ "Info" "ITDB_TH_RESULT" "multiplicand\[1\] word1\[1\] clock -2.439 ns register " "Info: th for register \"multiplicand\[1\]\" (data pin = \"word1\[1\]\", clock pin = \"clock\") is -2.439 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.452 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.637 ns) + CELL(0.618 ns) 2.452 ns multiplicand\[1\] 3 REG LCFF_X18_Y7_N3 2 " "Info: 3: + IC(0.637 ns) + CELL(0.618 ns) = 2.452 ns; Loc. = LCFF_X18_Y7_N3; Fanout = 2; REG Node = 'multiplicand\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.255 ns" { clock~clkctrl multiplicand[1] } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 60.03 % ) " "Info: Total cell delay = 1.472 ns ( 60.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.980 ns ( 39.97 % ) " "Info: Total interconnect delay = 0.980 ns ( 39.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.452 ns" { clock clock~clkctrl multiplicand[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.452 ns" { clock clock~combout clock~clkctrl multiplicand[1] } { 0.000ns 0.000ns 0.343ns 0.637ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 73 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.040 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.809 ns) 0.809 ns word1\[1\] 1 PIN PIN_AA13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_AA13; Fanout = 2; PIN Node = 'word1\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { word1[1] } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.922 ns) + CELL(0.309 ns) 5.040 ns multiplicand\[1\] 2 REG LCFF_X18_Y7_N3 2 " "Info: 2: + IC(3.922 ns) + CELL(0.309 ns) = 5.040 ns; Loc. = LCFF_X18_Y7_N3; Fanout = 2; REG Node = 'multiplicand\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.231 ns" { word1[1] multiplicand[1] } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.118 ns ( 22.18 % ) " "Info: Total cell delay = 1.118 ns ( 22.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.922 ns ( 77.82 % ) " "Info: Total interconnect delay = 3.922 ns ( 77.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.040 ns" { word1[1] multiplicand[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.040 ns" { word1[1] word1[1]~combout multiplicand[1] } { 0.000ns 0.000ns 3.922ns } { 0.000ns 0.809ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.452 ns" { clock clock~clkctrl multiplicand[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.452 ns" { clock clock~combout clock~clkctrl multiplicand[1] } { 0.000ns 0.000ns 0.343ns 0.637ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.040 ns" { word1[1] multiplicand[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.040 ns" { word1[1] word1[1]~combout multiplicand[1] } { 0.000ns 0.000ns 3.922ns } { 0.000ns 0.809ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 03 15:22:32 2009 " "Info: Processing ended: Sat Jan 03 15:22:32 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}