prev_cmp_multiplier.qmsg

乘法器 所占资源很少 很好的一个乘法器 史书上的一个例子 说得很好啊

{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/altera/Multiplier/Multiplier.fit.smsg " "Info: Generated suppressed messages file F:/altera/Multiplier/Multiplier.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "214 " "Info: Allocated 214 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 03 15:22:21 2009 " "Info: Processing ended: Sat Jan 03 15:22:21 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Web Edition " "Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 03 15:22:22 2009 " "Info: Processing started: Sat Jan 03 15:22:22 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Multiplier -c Multiplier " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Multiplier -c Multiplier" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "164 " "Info: Allocated 164 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 03 15:22:29 2009 " "Info: Processing ended: Sat Jan 03 15:22:29 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Web Edition " "Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 03 15:22:31 2009 " "Info: Processing started: Sat Jan 03 15:22:31 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Multiplier -c Multiplier --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Multiplier -c Multiplier --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 7 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register counter\[2\] register product\[4\]~reg0 498.75 MHz 2.005 ns Internal " "Info: Clock \"clock\" has Internal fmax of 498.75 MHz between source register \"counter\[2\]\" and destination register \"product\[4\]~reg0\" (period= 2.005 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.821 ns + Longest register register " "Info: + Longest register to register delay is 1.821 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[2\] 1 REG LCFF_X17_Y7_N23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y7_N23; Fanout = 3; REG Node = 'counter\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[2] } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.351 ns) + CELL(0.228 ns) 0.579 ns Equal2~84 2 COMB LCCOMB_X17_Y7_N16 3 " "Info: 2: + IC(0.351 ns) + CELL(0.228 ns) = 0.579 ns; Loc. = LCCOMB_X17_Y7_N16; Fanout = 3; COMB Node = 'Equal2~84'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.579 ns" { counter[2] Equal2~84 } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.218 ns) + CELL(0.053 ns) 0.850 ns product\[0\]~985 3 COMB LCCOMB_X17_Y7_N18 7 " "Info: 3: + IC(0.218 ns) + CELL(0.053 ns) = 0.850 ns; Loc. = LCCOMB_X17_Y7_N18; Fanout = 7; COMB Node = 'product\[0\]~985'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.271 ns" { Equal2~84 product[0]~985 } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.225 ns) + CELL(0.746 ns) 1.821 ns product\[4\]~reg0 4 REG LCFF_X17_Y7_N25 4 " "Info: 4: + IC(0.225 ns) + CELL(0.746 ns) = 1.821 ns; Loc. = LCFF_X17_Y7_N25; Fanout = 4; REG Node = 'product\[4\]~reg0'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.971 ns" { product[0]~985 product[4]~reg0 } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 73 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.027 ns ( 56.40 % ) " "Info: Total cell delay = 1.027 ns ( 56.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.794 ns ( 43.60 % ) " "Info: Total interconnect delay = 0.794 ns ( 43.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.821 ns" { counter[2] Equal2~84 product[0]~985 product[4]~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.821 ns" { counter[2] Equal2~84 product[0]~985 product[4]~reg0 } { 0.000ns 0.351ns 0.218ns 0.225ns } { 0.000ns 0.228ns 0.053ns 0.746ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.452 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.637 ns) + CELL(0.618 ns) 2.452 ns product\[4\]~reg0 3 REG LCFF_X17_Y7_N25 4 " "Info: 3: + IC(0.637 ns) + CELL(0.618 ns) = 2.452 ns; Loc. = LCFF_X17_Y7_N25; Fanout = 4; REG Node = 'product\[4\]~reg0'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.255 ns" { clock~clkctrl product[4]~reg0 } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 73 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 60.03 % ) " "Info: Total cell delay = 1.472 ns ( 60.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.980 ns ( 39.97 % ) " "Info: Total interconnect delay = 0.980 ns ( 39.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.452 ns" { clock clock~clkctrl product[4]~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.452 ns" { clock clock~combout clock~clkctrl product[4]~reg0 } { 0.000ns 0.000ns 0.343ns 0.637ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.452 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.637 ns) + CELL(0.618 ns) 2.452 ns counter\[2\] 3 REG LCFF_X17_Y7_N23 3 " "Info: 3: + IC(0.637 ns) + CELL(0.618 ns) = 2.452 ns; Loc. = LCFF_X17_Y7_N23; Fanout = 3; REG Node = 'counter\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.255 ns" { clock~clkctrl counter[2] } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 60.03 % ) " "Info: Total cell delay = 1.472 ns ( 60.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.980 ns ( 39.97 % ) " "Info: Total interconnect delay = 0.980 ns ( 39.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.452 ns" { clock clock~clkctrl counter[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.452 ns" { clock clock~combout clock~clkctrl counter[2] } { 0.000ns 0.000ns 0.343ns 0.637ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.452 ns" { clock clock~clkctrl product[4]~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.452 ns" { clock clock~combout clock~clkctrl product[4]~reg0 } { 0.000ns 0.000ns 0.343ns 0.637ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.452 ns" { clock clock~clkctrl counter[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.452 ns" { clock clock~combout clock~clkctrl counter[2] } { 0.000ns 0.000ns 0.343ns 0.637ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 73 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 73 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.821 ns" { counter[2] Equal2~84 product[0]~985 product[4]~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.821 ns" { counter[2] Equal2~84 product[0]~985 product[4]~reg0 } { 0.000ns 0.351ns 0.218ns 0.225ns } { 0.000ns 0.228ns 0.053ns 0.746ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.452 ns" { clock clock~clkctrl product[4]~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.452 ns" { clock clock~combout clock~clkctrl product[4]~reg0 } { 0.000ns 0.000ns 0.343ns 0.637ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.452 ns" { clock clock~clkctrl counter[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.452 ns" { clock clock~combout clock~clkctrl counter[2] } { 0.000ns 0.000ns 0.343ns 0.637ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "multiplicand\[0\] word1\[3\] clock 5.016 ns register " "Info: tsu for register \"multiplicand\[0\]\" (data pin = \"word1\[3\]\", clock pin = \"clock\") is 5.016 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.378 ns + Longest pin register " "Info: + Longest pin to register delay is 7.378 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.799 ns) 0.799 ns word1\[3\] 1 PIN PIN_C13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.799 ns) = 0.799 ns; Loc. = PIN_C13; Fanout = 2; PIN Node = 'word1\[3\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { word1[3] } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.625 ns) + CELL(0.346 ns) 5.770 ns Empty 2 COMB LCCOMB_X18_Y7_N26 3 " "Info: 2: + IC(4.625 ns) + CELL(0.346 ns) = 5.770 ns; Loc. = LCCOMB_X18_Y7_N26; Fanout = 3; COMB Node = 'Empty'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.971 ns" { word1[3] Empty } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.274 ns) + CELL(0.366 ns) 6.410 ns product\[0\]~980 3 COMB LCCOMB_X18_Y7_N10 8 " "Info: 3: + IC(0.274 ns) + CELL(0.366 ns) = 6.410 ns; Loc. = LCCOMB_X18_Y7_N10; Fanout = 8; COMB Node = 'product\[0\]~980'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.640 ns" { Empty product[0]~980 } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.222 ns) + CELL(0.746 ns) 7.378 ns multiplicand\[0\] 4 REG LCFF_X18_Y7_N1 2 " "Info: 4: + IC(0.222 ns) + CELL(0.746 ns) = 7.378 ns; Loc. = LCFF_X18_Y7_N1; Fanout = 2; REG Node = 'multiplicand\[0\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.968 ns" { product[0]~980 multiplicand[0] } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.257 ns ( 30.59 % ) " "Info: Total cell delay = 2.257 ns ( 30.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.121 ns ( 69.41 % ) " "Info: Total interconnect delay = 5.121 ns ( 69.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.378 ns" { word1[3] Empty product[0]~980 multiplicand[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.378 ns" { word1[3] word1[3]~combout Empty product[0]~980 multiplicand[0] } { 0.000ns 0.000ns 4.625ns 0.274ns 0.222ns } { 0.000ns 0.799ns 0.346ns 0.366ns 0.746ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 73 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.452 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: