prev_cmp_multiplier.qmsg

乘法器 所占资源很少 很好的一个乘法器 史书上的一个例子 说得很好啊

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Web Edition " "Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 03 15:22:11 2009 " "Info: Processing started: Sat Jan 03 15:22:11 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Multiplier -c Multiplier " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Multiplier -c Multiplier" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Multiplier.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Multiplier.v" { { "Info" "ISGN_ENTITY_NAME" "1 Multiplier " "Info: Found entity 1: Multiplier" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Multiplier " "Info: Elaborating entity \"Multiplier\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 Multiplier.v(20) " "Warning (10230): Verilog HDL assignment warning at Multiplier.v(20): truncated value with size 32 to match size of target (1)" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 Multiplier.v(29) " "Warning (10230): Verilog HDL assignment warning at Multiplier.v(29): truncated value with size 32 to match size of target (1)" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 Multiplier.v(31) " "Warning (10230): Verilog HDL assignment warning at Multiplier.v(31): truncated value with size 32 to match size of target (1)" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 31 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 Multiplier.v(34) " "Warning (10230): Verilog HDL assignment warning at Multiplier.v(34): truncated value with size 32 to match size of target (1)" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 34 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 Multiplier.v(36) " "Warning (10230): Verilog HDL assignment warning at Multiplier.v(36): truncated value with size 32 to match size of target (1)" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 36 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 Multiplier.v(41) " "Warning (10230): Verilog HDL assignment warning at Multiplier.v(41): truncated value with size 32 to match size of target (1)" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 41 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 Multiplier.v(43) " "Warning (10230): Verilog HDL assignment warning at Multiplier.v(43): truncated value with size 32 to match size of target (1)" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 43 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 Multiplier.v(45) " "Warning (10230): Verilog HDL assignment warning at Multiplier.v(45): truncated value with size 32 to match size of target (1)" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 45 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 Multiplier.v(72) " "Warning (10230): Verilog HDL assignment warning at Multiplier.v(72): truncated value with size 32 to match size of target (3)" {  } { { "Multiplier.v" "" { Text "F:/altera/Multiplier/Multiplier.v" 72 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}