📄 multiplier.tan.rpt
字号:
; N/A ; None ; -4.201 ns ; word2[3] ; product[0]~reg0 ; clock ;
; N/A ; None ; -4.203 ns ; word2[3] ; product[2]~reg0 ; clock ;
; N/A ; None ; -4.222 ns ; word1[2] ; counter[0] ; clock ;
; N/A ; None ; -4.223 ns ; word1[2] ; counter[2] ; clock ;
; N/A ; None ; -4.261 ns ; word2[0] ; product[3]~reg0 ; clock ;
; N/A ; None ; -4.270 ns ; word2[2] ; multiplicand[0] ; clock ;
; N/A ; None ; -4.270 ns ; word2[2] ; multiplicand[1] ; clock ;
; N/A ; None ; -4.270 ns ; word2[2] ; multiplicand[2] ; clock ;
; N/A ; None ; -4.270 ns ; word2[2] ; multiplicand[3] ; clock ;
; N/A ; None ; -4.270 ns ; word2[0] ; product[1]~reg0 ; clock ;
; N/A ; None ; -4.333 ns ; word1[3] ; counter[0] ; clock ;
; N/A ; None ; -4.334 ns ; word1[3] ; counter[2] ; clock ;
; N/A ; None ; -4.337 ns ; word2[1] ; product[0]~reg0 ; clock ;
; N/A ; None ; -4.339 ns ; word2[1] ; product[2]~reg0 ; clock ;
; N/A ; None ; -4.346 ns ; word2[0] ; multiplicand[0] ; clock ;
; N/A ; None ; -4.346 ns ; word2[0] ; multiplicand[1] ; clock ;
; N/A ; None ; -4.346 ns ; word2[0] ; multiplicand[2] ; clock ;
; N/A ; None ; -4.346 ns ; word2[0] ; multiplicand[3] ; clock ;
; N/A ; None ; -4.351 ns ; word2[3] ; product[1]~reg0 ; clock ;
; N/A ; None ; -4.427 ns ; word2[3] ; multiplicand[0] ; clock ;
; N/A ; None ; -4.427 ns ; word2[3] ; multiplicand[1] ; clock ;
; N/A ; None ; -4.427 ns ; word2[3] ; multiplicand[2] ; clock ;
; N/A ; None ; -4.427 ns ; word2[3] ; multiplicand[3] ; clock ;
; N/A ; None ; -4.440 ns ; word1[2] ; product[0]~reg0 ; clock ;
; N/A ; None ; -4.442 ns ; word1[2] ; product[2]~reg0 ; clock ;
; N/A ; None ; -4.478 ns ; word2[1] ; product[3]~reg0 ; clock ;
; N/A ; None ; -4.551 ns ; word1[3] ; product[0]~reg0 ; clock ;
; N/A ; None ; -4.553 ns ; word1[3] ; product[2]~reg0 ; clock ;
; N/A ; None ; -4.563 ns ; word2[1] ; multiplicand[0] ; clock ;
; N/A ; None ; -4.563 ns ; word2[1] ; multiplicand[1] ; clock ;
; N/A ; None ; -4.563 ns ; word2[1] ; multiplicand[2] ; clock ;
; N/A ; None ; -4.563 ns ; word2[1] ; multiplicand[3] ; clock ;
; N/A ; None ; -4.581 ns ; word1[2] ; product[3]~reg0 ; clock ;
; N/A ; None ; -4.590 ns ; word1[2] ; product[1]~reg0 ; clock ;
; N/A ; None ; -4.666 ns ; word1[2] ; multiplicand[0] ; clock ;
; N/A ; None ; -4.666 ns ; word1[2] ; multiplicand[1] ; clock ;
; N/A ; None ; -4.666 ns ; word1[2] ; multiplicand[3] ; clock ;
; N/A ; None ; -4.692 ns ; word1[3] ; product[3]~reg0 ; clock ;
; N/A ; None ; -4.701 ns ; word1[3] ; product[1]~reg0 ; clock ;
; N/A ; None ; -4.777 ns ; word1[3] ; multiplicand[0] ; clock ;
; N/A ; None ; -4.777 ns ; word1[3] ; multiplicand[1] ; clock ;
; N/A ; None ; -4.777 ns ; word1[3] ; multiplicand[2] ; clock ;
+---------------+-------------+-----------+----------+-----------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
Info: Processing started: Sat Jan 03 15:22:59 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Multiplier -c Multiplier --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 498.75 MHz between source register "counter[2]" and destination register "product[4]~reg0" (period= 2.005 ns)
Info: + Longest register to register delay is 1.821 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y7_N23; Fanout = 3; REG Node = 'counter[2]'
Info: 2: + IC(0.351 ns) + CELL(0.228 ns) = 0.579 ns; Loc. = LCCOMB_X17_Y7_N16; Fanout = 3; COMB Node = 'Equal2~84'
Info: 3: + IC(0.218 ns) + CELL(0.053 ns) = 0.850 ns; Loc. = LCCOMB_X17_Y7_N18; Fanout = 7; COMB Node = 'product[0]~985'
Info: 4: + IC(0.225 ns) + CELL(0.746 ns) = 1.821 ns; Loc. = LCFF_X17_Y7_N25; Fanout = 4; REG Node = 'product[4]~reg0'
Info: Total cell delay = 1.027 ns ( 56.40 % )
Info: Total interconnect delay = 0.794 ns ( 43.60 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clock" to destination register is 2.452 ns
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.637 ns) + CELL(0.618 ns) = 2.452 ns; Loc. = LCFF_X17_Y7_N25; Fanout = 4; REG Node = 'product[4]~reg0'
Info: Total cell delay = 1.472 ns ( 60.03 % )
Info: Total interconnect delay = 0.980 ns ( 39.97 % )
Info: - Longest clock path from clock "clock" to source register is 2.452 ns
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.637 ns) + CELL(0.618 ns) = 2.452 ns; Loc. = LCFF_X17_Y7_N23; Fanout = 3; REG Node = 'counter[2]'
Info: Total cell delay = 1.472 ns ( 60.03 % )
Info: Total interconnect delay = 0.980 ns ( 39.97 % )
Info: + Micro clock to output delay of source is 0.094 ns
Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "multiplicand[0]" (data pin = "word1[3]", clock pin = "clock") is 5.016 ns
Info: + Longest pin to register delay is 7.378 ns
Info: 1: + IC(0.000 ns) + CELL(0.799 ns) = 0.799 ns; Loc. = PIN_C13; Fanout = 2; PIN Node = 'word1[3]'
Info: 2: + IC(4.625 ns) + CELL(0.346 ns) = 5.770 ns; Loc. = LCCOMB_X18_Y7_N26; Fanout = 3; COMB Node = 'Empty'
Info: 3: + IC(0.274 ns) + CELL(0.366 ns) = 6.410 ns; Loc. = LCCOMB_X18_Y7_N10; Fanout = 8; COMB Node = 'product[0]~980'
Info: 4: + IC(0.222 ns) + CELL(0.746 ns) = 7.378 ns; Loc. = LCFF_X18_Y7_N1; Fanout = 2; REG Node = 'multiplicand[0]'
Info: Total cell delay = 2.257 ns ( 30.59 % )
Info: Total interconnect delay = 5.121 ns ( 69.41 % )
Info: + Micro setup delay of destination is 0.090 ns
Info: - Shortest clock path from clock "clock" to destination register is 2.452 ns
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.637 ns) + CELL(0.618 ns) = 2.452 ns; Loc. = LCFF_X18_Y7_N1; Fanout = 2; REG Node = 'multiplicand[0]'
Info: Total cell delay = 1.472 ns ( 60.03 % )
Info: Total interconnect delay = 0.980 ns ( 39.97 % )
Info: tco from clock "clock" to destination pin "product[2]" through register "product[2]~reg0" is 6.527 ns
Info: + Longest clock path from clock "clock" to source register is 2.452 ns
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.637 ns) + CELL(0.618 ns) = 2.452 ns; Loc. = LCFF_X17_Y7_N15; Fanout = 2; REG Node = 'product[2]~reg0'
Info: Total cell delay = 1.472 ns ( 60.03 % )
Info: Total interconnect delay = 0.980 ns ( 39.97 % )
Info: + Micro clock to output delay of source is 0.094 ns
Info: + Longest register to pin delay is 3.981 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y7_N15; Fanout = 2; REG Node = 'product[2]~reg0'
Info: 2: + IC(1.827 ns) + CELL(2.154 ns) = 3.981 ns; Loc. = PIN_U2; Fanout = 0; PIN Node = 'product[2]'
Info: Total cell delay = 2.154 ns ( 54.11 % )
Info: Total interconnect delay = 1.827 ns ( 45.89 % )
Info: Longest tpd from source pin "reset" to destination pin "Ready" is 8.445 ns
Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 2; PIN Node = 'reset'
Info: 2: + IC(4.516 ns) + CELL(0.225 ns) = 5.605 ns; Loc. = LCCOMB_X18_Y7_N24; Fanout = 1; COMB Node = 'comb~0'
Info: 3: + IC(0.842 ns) + CELL(1.998 ns) = 8.445 ns; Loc. = PIN_Y12; Fanout = 0; PIN Node = 'Ready'
Info: Total cell delay = 3.087 ns ( 36.55 % )
Info: Total interconnect delay = 5.358 ns ( 63.45 % )
Info: th for register "multiplicand[1]" (data pin = "word1[1]", clock pin = "clock") is -2.439 ns
Info: + Longest clock path from clock "clock" to destination register is 2.452 ns
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.637 ns) + CELL(0.618 ns) = 2.452 ns; Loc. = LCFF_X18_Y7_N3; Fanout = 2; REG Node = 'multiplicand[1]'
Info: Total cell delay = 1.472 ns ( 60.03 % )
Info: Total interconnect delay = 0.980 ns ( 39.97 % )
Info: + Micro hold delay of destination is 0.149 ns
Info: - Shortest pin to register delay is 5.040 ns
Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_AA13; Fanout = 2; PIN Node = 'word1[1]'
Info: 2: + IC(3.922 ns) + CELL(0.309 ns) = 5.040 ns; Loc. = LCFF_X18_Y7_N3; Fanout = 2; REG Node = 'multiplicand[1]'
Info: Total cell delay = 1.118 ns ( 22.18 % )
Info: Total interconnect delay = 3.922 ns ( 77.82 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 112 megabytes of memory during processing
Info: Processing ended: Sat Jan 03 15:22:59 2009
Info: Elapsed time: 00:00:00
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