程序.txt

好用的函数信号发生器

--递增锯齿波的程序设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dai_dzjc is
port(clk,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end dai_dzjc;
architecture a of dai_dzjc is
begin
process(clk,reset)
variable tmp:std_logic_vector(7 downto 0);
begin
if reset='0' then
tmp:="00000000";
else if clk'event and clk='1' then
if tmp="11111111" then
tmp:="00000000";
else
tmp:=tmp+1;
end if;
end if;
end if;
q<=tmp;
end process;
end a;

--递减锯齿波的程序设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dai_djjc is
port(clk,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end dai_dzjjc;
architecture a of dai_djjc is
begin
process(clk,reset)
variable tmp:std_logic_vector(7 downto 0);
begin
if reset='0' then
tmp:="11111111";
else if clk'event and clk='1' then
if tmp="00000000" then
tmp:="11111111";
else
tmp:=tmp-1;
end if;
end if;
end if;
q<=tmp;
end process;
end a;

--三角波的程序设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dai_sj is
port(clk,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end dai_sj;
architecture a of dai_sj is
begin
process(clk,reset)
variable tmp:std_logic_vector(7 downto 0);
variable a:std_logic;
begin
if reset='0' then
tmp:="00000000";
else if clk'event and clk='1' then
if a='0' then
if tmp="11111110" then
tmp:="11111111";
a:='1';
else
tmp:=tmp+1;
end if;
else
if tmp="00000001" then
tmp:="00000000";
a:='0';
else
tmp:=tmp-1;
end if;
end if;
end if;
end if;
q<=tmp;
end process;
end a;

--梯形波
LIBRARY IEEE;
USE IEEE. STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY xl_trap IS    
  PORT (clk,reset: IN STD_LOGIC;
        q:OUT integer RANGE 0 to 255 );--STD_LOGIC_VECTOR (7 DOWNTO 0));
END xl_trap;
ARCHITECTURE behave OF xl_trap IS
BEGIN
   PROCESS (clk,reset)
   VARIABLE tmp,a: integer RANGE 0 to 255;--STD_LOGIC_VECTOR (7 DOWNTO 0);
   BEGIN
      IF reset='0' THEN
        tmp:=0;
        a:=0;
      ELSIF clk'EVENT AND clk='1'THEN
         if a=255 then a:=0;tmp:=0;
          else a:=a+1;
         end if;
       case a is
        when 1 to 63 => tmp:=tmp+4;
        when 64 to 127 => tmp:=255;          
        when 128 to 190 => tmp:= tmp-4; 
        when 192 to 255 => tmp:=0; 
        when others => tmp:=0; 
       end case;
         END IF;
         q<=tmp;
      END PROCESS;
    END behave;



--方波的程序设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dai_fb is
port(clk,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end dai_fb;
architecture a of dai_fb is
signal a: std_logic;
begin
process(clk,reset)
variable tmp:std_logic_vector(7 downto 0);
begin
if reset='0' then
a<='0';
else if clk'event and clk='1' then
if tmp="11111111" then
tmp:="00000000";
else
tmp:=tmp+1;
end if;
if tmp<"10000000" then
a<='1';
else
a<='0';
end if;
end if;
end if;
end process;
process(clk,a)
begin
if clk'event and clk='1' then
if a='1' then
q<="11111111";
else
q<="00000000";
end if;
end if;
end process;
end a;



--正弦波产生程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dai_zx IS
PORT(CLK,clr:IN STD_LOGIC;
     d:OUT integer range 0 to 255 );
END dai_zx;
architecture behave of dai_zx is
begin
process(clk,clr)
variable b: integer range 0 to 63;
begin
if clr='0' then
d<=0;
elsif rising_edge(clk) then
if b=63 then  --一个周期取64个点
b:=0;
else
b:=b+1;
end if;
case b is            --查表输出
when 00=>d<=255;when 01=>d<=254;when 02=>d<=252;when 03=>d<=249;
when 04=>d<=245;when 05=>d<=239;when 06=>d<=233;when 07=>d<=225;
when 08=>d<=217;when 09=>d<=207;when 10=>d<=197;when 11=>d<=186;
when 12=>d<=174;when 13=>d<=162;when 14=>d<=150;when 15=>d<=137;
when 16=>d<=124;when 17=>d<=112;when 18=>d<=99;when 19=>d<=87;
when 20=>d<=75;when 21=>d<=64;when 22=>d<=53;when 23=>d<=43;
when 24=>d<=34;when 25=>d<=26;when 26=>d<=19;when 27=>d<=13;
when 28=>d<=8;when 29=>d<=4;when 30=>d<=1;when 31=>d<=0;
when 32=>d<=0;when 33=>d<=1;when 34=>d<=4;when 35=>d<=8;
when 36=>d<=13;when 37=>d<=19;when 38=>d<=26;when 39=>d<=34;
when 40=>d<=43;when 41=>d<=53;when 42=>d<=64;when 43=>d<=75;
when 44=>d<=87;when 45=>d<=99;when 46=>d<=112;when 47=>d<=124;
when 48=>d<=137;when 49=>d<=150;when 50=>d<=162;when 51=>d<=174;
when 52=>d<=186;when 53=>d<=197;when 54=>d<=207;when 55=>d<=217;
when 56=>d<=225;when 57=>d<=233;when 58=>d<=239;when 59=>d<=245;
when 60=>d<=249;when 61=>d<=252;when 62=>d<=254;when 63=>d<=255;
when others=>null;
end case;
end if;
end process;
end behave;


--数据选择器的程序设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux6_1 is
port(sel:in std_logic_vector(2 downto 0);
d1,d2,d3,d4,d5,d6:in std_logic_vector(7 downto 0);
q: out std_logic_vector(7 downto 0));
end mux6_1;
architecture a of mux6_1 is
begin
process(sel)
begin
case sel is
when "001"=>q<=d1;
when "010"=>q<=d2;
when "011"=>q<=d3;
when "100"=>q<=d4;
when "101"=>q<=d5;
when "110"=>q<=d6;
when others=>null;
end case;
end process;
end a;