div.map.summary

来自「FPGA调试程序」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Tue Nov 25 10:37:59 2008
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : div
Top-level Entity Name : div
Family : ACEX1K
Total logic elements : 73
Total pins : 7
Total memory bits : 0
Total PLLs : 0