div.v

来自「FPGA调试程序」· Verilog 代码 · 共 25 行

module		div(
					clk,
					leda		
					);

input		clk;
output		[5:0]leda;

reg		[5:0]leda;

parameter	MAX	= 50_000;
			
integer		count;

always @(posedge clk)
begin
		if( count == MAX )
		begin
			count <= 0;
			leda <= ~leda;
		end
		else
			count <= count + 1'b1;	
end
endmodule