div.map.rpt

FPGA调试程序

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                     ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------+
; Compilation Hierarchy Node         ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                         ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------+
; |div                               ; 73 (42)     ; 33           ; 0           ; 7    ; 40 (9)       ; 25 (25)           ; 8 (8)            ; 32 (1)          ; 0 (0)      ; |div                                                        ;
;    |lpm_add_sub:Add0|              ; 31 (0)      ; 0            ; 0           ; 0    ; 31 (0)       ; 0 (0)             ; 0 (0)            ; 31 (0)          ; 0 (0)      ; |div|lpm_add_sub:Add0                                       ;
;       |addcore:adder|              ; 31 (1)      ; 0            ; 0           ; 0    ; 31 (1)       ; 0 (0)             ; 0 (0)            ; 31 (1)          ; 0 (0)      ; |div|lpm_add_sub:Add0|addcore:adder                         ;
;          |a_csnbuffer:result_node| ; 30 (30)     ; 0            ; 0           ; 0    ; 30 (30)      ; 0 (0)             ; 0 (0)            ; 30 (30)         ; 0 (0)      ; |div|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------+
; Registers Removed During Synthesis                               ;
+---------------------------------------+--------------------------+
; Register name                         ; Reason for Removal       ;
+---------------------------------------+--------------------------+
; leda[4]~reg0                          ; Merged with leda[0]~reg0 ;
; leda[1]~reg0                          ; Merged with leda[0]~reg0 ;
; leda[3]~reg0                          ; Merged with leda[0]~reg0 ;
; leda[5]~reg0                          ; Merged with leda[0]~reg0 ;
; leda[2]~reg0                          ; Merged with leda[0]~reg0 ;
; Total Number of Removed Registers = 5 ;                          ;
+---------------------------------------+--------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 33    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 1     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |div ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type                                       ;
+----------------+-------+--------------------------------------------+
; MAX            ; 50000 ; Signed Integer                             ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0 ;
+------------------------+-------------+----------------------------+
; Parameter Name         ; Value       ; Type                       ;
+------------------------+-------------+----------------------------+
; LPM_WIDTH              ; 32          ; Untyped                    ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                    ;
; LPM_DIRECTION          ; ADD         ; Untyped                    ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                    ;
; LPM_PIPELINE           ; 0           ; Untyped                    ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                    ;
; REGISTERED_AT_END      ; 0           ; Untyped                    ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                    ;
; USE_CS_BUFFERS         ; 1           ; Untyped                    ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                    ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH         ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                    ;
; USE_WYS                ; OFF         ; Untyped                    ;
; STYLE                  ; FAST        ; Untyped                    ;
; CBXI_PARAMETER         ; add_sub_5nh ; Untyped                    ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                 ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY               ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE               ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE             ;
+------------------------+-------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Nov 25 10:37:57 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off div -c div
Info: Found 1 design units, including 1 entities, in source file div.v
    Info: Found entity 1: div
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Elaborating entity "div" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0"
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/quartus/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/quartus/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/quartus/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Duplicate registers merged to single register
    Info: Duplicate register "leda[4]~reg0" merged to single register "leda[0]~reg0"
    Info: Duplicate register "leda[1]~reg0" merged to single register "leda[0]~reg0"
    Info: Duplicate register "leda[3]~reg0" merged to single register "leda[0]~reg0"
    Info: Duplicate register "leda[5]~reg0" merged to single register "leda[0]~reg0"
    Info: Duplicate register "leda[2]~reg0" merged to single register "leda[0]~reg0"
Info: Implemented 80 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 6 output pins
    Info: Implemented 73 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 123 megabytes of memory during processing
    Info: Processing ended: Tue Nov 25 10:37:59 2008
    Info: Elapsed time: 00:00:02