vgatiming.vhd

此乃VGA驱动的详细源码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity vgatiming is
    Port ( clk : in std_logic;
         reset : in std_logic;
           hs  : buffer std_logic;         --行同步
           vs  : out std_logic;         --场同步
           red : out std_logic;
         green : out std_logic;
          blue : out std_logic);
end vgatiming;

architecture Behavioral of vgatiming is

constant H_PIXELS: INTEGER:=640;
constant H_FRONT: INTEGER:=16;
constant H_BACK: INTEGER:=48;
constant H_SYNCTIME: INTEGER:=96;
constant H_PERIOD: INTEGER:= H_SYNCTIME + H_PIXELS + H_FRONT + H_BACK;

-- vertical timing signals
constant V_LINES: INTEGER:=480;
constant V_FRONT: INTEGER:=11;
constant V_BACK: INTEGER:=32;
constant V_SYNCTIME: INTEGER:=2;
constant V_PERIOD: INTEGER:= V_SYNCTIME + V_LINES + V_FRONT + V_BACK;
  signal  hs_cnt : std_logic_vector(9 downto 0);
  signal  hs_xy  : std_logic;
  --signal  hs_xy_cnt  :std_logic_vector(9 downto 0);--行消隐
  signal  vs_cnt : std_logic_vector(9 downto 0);
  signal  vs_xy  : std_logic;
 -- signal  vs_xy_cnt  :std_logic_vector(9 downto 0);--行消隐
 begin
      red<='1';
      green<='0';
      blue<='0';
-- control the reset, increment and overflow of the horizontal pixel count
A: process(clk, reset)
begin
	-- reset asynchronously clears horizontal counter
	if reset = '0' then
		hs_cnt <= (others => '0');
	-- horiz. counter increments on rising edge of dot clock
	elsif (clk'event and clk = '1') then
		-- horiz. counter restarts after the horizontal period (set by the constants)
		if hs_cnt < H_PERIOD then
			hs_cnt <= hs_cnt + 1;
		else
			hs_cnt <= (others => '0');
		end if;
	end if;
end process;

-- control the reset, increment and overflow of the vertical line counter after every horizontal line
B: process(hs, reset)
begin
	-- reset asynchronously clears line counter
	if reset='0' then
		vs_cnt <= (others => '0');
	-- vert. line counter increments after every horiz. line
	elsif (hs'event and hs = '1') then
		-- vert. line counter rolls-over after the set number of lines (set by the constants)
		if vs_cnt < V_PERIOD then
			vs_cnt <= vs_cnt + 1;
		else
			vs_cnt <= (others => '0');
		end if;
	end if;
end process;

-- set the horizontal sync high time and low time according to the constants
C: process(clk, reset)
begin
	-- reset asynchronously sets horizontal sync to inactive
	if reset = '0' then
		hs_xy  <= '1';
	-- horizontal sync is recomputed on the rising edge of every dot clock
	elsif (clk'event and clk = '1') then
		-- horiz. sync is low in this interval to signal start of a new line
		if (hs_cnt >= (H_PIXELS + H_FRONT) and hs_cnt < (H_PIXELS + H_SYNCTIME + H_FRONT)) then
			hs_xy  <= '0';

		else
			hs_xy  <= '1';

		end if;
	end if;
end process;

-- set the vertical sync high time and low time according to the constants
D: process(clk, reset,hs)
begin
	-- reset asynchronously sets vertical sync to inactive
	if reset = '0' then
		vs_xy <= '1';
	 --vertical sync is recomputed at the end of every line of pixels
	elsif (hs'event and hs = '1') then
		-- vert. sync is low in this interval to signal start of a new frame
		if (vs_cnt >= (V_LINES + V_FRONT) and vs_cnt < (V_LINES + V_SYNCTIME + V_FRONT)) then
			vs_xy <= '0';
		else
			vs_xy <= '1';
		end if;
	end if;
end process;
hs<=hs_xy;
vs<=vs_xy;
-- whether it should latch the current data or not
  end Behavioral;