📄 vga.map.rpt
字号:
; G0_INITIAL ; 1 ; Untyped ;
; G1_INITIAL ; 1 ; Untyped ;
; G2_INITIAL ; 1 ; Untyped ;
; G3_INITIAL ; 1 ; Untyped ;
; E0_INITIAL ; 1 ; Untyped ;
; E1_INITIAL ; 1 ; Untyped ;
; E2_INITIAL ; 1 ; Untyped ;
; E3_INITIAL ; 1 ; Untyped ;
; L0_MODE ; BYPASS ; Untyped ;
; L1_MODE ; BYPASS ; Untyped ;
; G0_MODE ; BYPASS ; Untyped ;
; G1_MODE ; BYPASS ; Untyped ;
; G2_MODE ; BYPASS ; Untyped ;
; G3_MODE ; BYPASS ; Untyped ;
; E0_MODE ; BYPASS ; Untyped ;
; E1_MODE ; BYPASS ; Untyped ;
; E2_MODE ; BYPASS ; Untyped ;
; E3_MODE ; BYPASS ; Untyped ;
; L0_PH ; 0 ; Untyped ;
; L1_PH ; 0 ; Untyped ;
; G0_PH ; 0 ; Untyped ;
; G1_PH ; 0 ; Untyped ;
; G2_PH ; 0 ; Untyped ;
; G3_PH ; 0 ; Untyped ;
; E0_PH ; 0 ; Untyped ;
; E1_PH ; 0 ; Untyped ;
; E2_PH ; 0 ; Untyped ;
; E3_PH ; 0 ; Untyped ;
; M_PH ; 0 ; Untyped ;
; C1_USE_CASC_IN ; 0 ; Untyped ;
; C2_USE_CASC_IN ; 0 ; Untyped ;
; C3_USE_CASC_IN ; 0 ; Untyped ;
; C4_USE_CASC_IN ; 0 ; Untyped ;
; C5_USE_CASC_IN ; 0 ; Untyped ;
; CLK0_COUNTER ; G0 ; Untyped ;
; CLK1_COUNTER ; G0 ; Untyped ;
; CLK2_COUNTER ; G0 ; Untyped ;
; CLK3_COUNTER ; G0 ; Untyped ;
; CLK4_COUNTER ; G0 ; Untyped ;
; CLK5_COUNTER ; G0 ; Untyped ;
; L0_TIME_DELAY ; 0 ; Untyped ;
; L1_TIME_DELAY ; 0 ; Untyped ;
; G0_TIME_DELAY ; 0 ; Untyped ;
; G1_TIME_DELAY ; 0 ; Untyped ;
; G2_TIME_DELAY ; 0 ; Untyped ;
; G3_TIME_DELAY ; 0 ; Untyped ;
; E0_TIME_DELAY ; 0 ; Untyped ;
; E1_TIME_DELAY ; 0 ; Untyped ;
; E2_TIME_DELAY ; 0 ; Untyped ;
; E3_TIME_DELAY ; 0 ; Untyped ;
; M_TIME_DELAY ; 0 ; Untyped ;
; N_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_COUNTER ; E3 ; Untyped ;
; EXTCLK2_COUNTER ; E2 ; Untyped ;
; EXTCLK1_COUNTER ; E1 ; Untyped ;
; EXTCLK0_COUNTER ; E0 ; Untyped ;
; ENABLE0_COUNTER ; L0 ; Untyped ;
; ENABLE1_COUNTER ; L0 ; Untyped ;
; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
; LOOP_FILTER_R ; 1.000000 ; Untyped ;
; LOOP_FILTER_C ; 5 ; Untyped ;
; VCO_POST_SCALE ; 0 ; Untyped ;
; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; INTENDED_DEVICE_FAMILY ; Cyclone II ; Untyped ;
; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ;
; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+-------------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/vga/vga.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Thu May 24 11:39:02 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga -c vga
Info: Found 1 design units, including 1 entities, in source file vga.bdf
Info: Found entity 1: vga
Info: Found 2 design units, including 1 entities, in source file vgatiming.vhd
Info: Found design unit 1: vgatiming-Behavioral
Info: Found entity 1: vgatiming
Info: Elaborating entity "vga" for the top level hierarchy
Warning: Pin "pin_name5" overlaps another pin, block, or symbol
Warning: Port "hs" of type vgatiming and instance "inst" is missing source signal
Warning: Pin "vs" is missing source
Info: Elaborating entity "vgatiming" for hierarchy "vgatiming:inst"
Warning: Using design file pll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: pll-SYN
Info: Found entity 1: pll
Info: Elaborating entity "pll" for hierarchy "pll:inst5"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altpll.tdf
Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "pll:inst5|altpll:altpll_component"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Output pins are stuck at VCC or GND
Warning: Pin "vs" stuck at GND
Warning: Pin "r" stuck at VCC
Warning: Pin "g" stuck at GND
Warning: Pin "b" stuck at GND
Info: Implemented 40 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 6 output pins
Info: Implemented 31 logic cells
Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
Info: Processing ended: Thu May 24 11:39:06 2007
Info: Elapsed time: 00:00:05
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