vga.tan.rpt

此乃VGA驱动的详细源码

; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                          ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                         ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; pll:inst5|altpll:altpll_component|_clk0 ;                    ; PLL output ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; clk      ; 1                     ; 1                   ; -2.290 ns ;              ;
; clk                                     ;                    ; User Pin   ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pll:inst5|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                      ;
+-----------------------------------------+-----------------------------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                     ; To                       ; From Clock                              ; To Clock                                ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
; 35.895 ns                               ; 243.61 MHz ( period = 4.105 ns )                    ; vgatiming:inst|vs_cnt[1] ; vgatiming:inst|vs_cnt[9] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.841 ns                ;
; 35.895 ns                               ; 243.61 MHz ( period = 4.105 ns )                    ; vgatiming:inst|vs_cnt[1] ; vgatiming:inst|vs_cnt[2] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.841 ns                ;
; 35.895 ns                               ; 243.61 MHz ( period = 4.105 ns )                    ; vgatiming:inst|vs_cnt[1] ; vgatiming:inst|vs_cnt[1] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.841 ns                ;
; 35.895 ns                               ; 243.61 MHz ( period = 4.105 ns )                    ; vgatiming:inst|vs_cnt[1] ; vgatiming:inst|vs_cnt[0] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.841 ns                ;
; 35.895 ns                               ; 243.61 MHz ( period = 4.105 ns )                    ; vgatiming:inst|vs_cnt[1] ; vgatiming:inst|vs_cnt[3] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.841 ns                ;
; 35.895 ns                               ; 243.61 MHz ( period = 4.105 ns )                    ; vgatiming:inst|vs_cnt[1] ; vgatiming:inst|vs_cnt[8] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.841 ns                ;
; 35.895 ns                               ; 243.61 MHz ( period = 4.105 ns )                    ; vgatiming:inst|vs_cnt[1] ; vgatiming:inst|vs_cnt[5] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.841 ns                ;
; 35.895 ns                               ; 243.61 MHz ( period = 4.105 ns )                    ; vgatiming:inst|vs_cnt[1] ; vgatiming:inst|vs_cnt[6] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.841 ns                ;
; 35.895 ns                               ; 243.61 MHz ( period = 4.105 ns )                    ; vgatiming:inst|vs_cnt[1] ; vgatiming:inst|vs_cnt[7] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.841 ns                ;
; 35.895 ns                               ; 243.61 MHz ( period = 4.105 ns )                    ; vgatiming:inst|vs_cnt[1] ; vgatiming:inst|vs_cnt[4] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.841 ns                ;
; 36.069 ns                               ; 254.39 MHz ( period = 3.931 ns )                    ; vgatiming:inst|vs_cnt[0] ; vgatiming:inst|vs_cnt[9] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.667 ns                ;
; 36.069 ns                               ; 254.39 MHz ( period = 3.931 ns )                    ; vgatiming:inst|vs_cnt[0] ; vgatiming:inst|vs_cnt[2] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.667 ns                ;
; 36.069 ns                               ; 254.39 MHz ( period = 3.931 ns )                    ; vgatiming:inst|vs_cnt[0] ; vgatiming:inst|vs_cnt[1] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.667 ns                ;
; 36.069 ns                               ; 254.39 MHz ( period = 3.931 ns )                    ; vgatiming:inst|vs_cnt[0] ; vgatiming:inst|vs_cnt[0] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.667 ns                ;
; 36.069 ns                               ; 254.39 MHz ( period = 3.931 ns )                    ; vgatiming:inst|vs_cnt[0] ; vgatiming:inst|vs_cnt[3] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.667 ns                ;
; 36.069 ns                               ; 254.39 MHz ( period = 3.931 ns )                    ; vgatiming:inst|vs_cnt[0] ; vgatiming:inst|vs_cnt[8] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 3.667 ns                ;